37 lines · plain
1; RUN: llc -mtriple=hexagon -O2 < %s2; REQUIRES: asserts3 4define inreg <16 x i32> @f0(i32 %a0, ptr nocapture %a1) #0 {5b0:6 %v0 = tail call <64 x i1> @llvm.hexagon.V6.pred.scalar2(i32 %a0)7 %v1 = tail call <64 x i1> @llvm.hexagon.V6.pred.not(<64 x i1> %v0)8 %v2 = icmp ult i32 %a0, 489 br i1 %v2, label %b1, label %b210 11b1: ; preds = %b012 %v3 = add nuw nsw i32 %a0, 1613 %v4 = tail call <64 x i1> @llvm.hexagon.V6.pred.scalar2(i32 %v3)14 %v5 = tail call <64 x i1> @llvm.hexagon.V6.pred.and(<64 x i1> %v4, <64 x i1> %v1)15 br label %b216 17b2: ; preds = %b1, %b018 %v6 = phi <64 x i1> [ %v5, %b1 ], [ %v1, %b0 ]19 %v7 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %v6, i32 -1)20 %v8 = getelementptr inbounds <16 x i32>, ptr %a1, i32 121 %v9 = load <16 x i32>, ptr %v8, align 6422 %v10 = getelementptr inbounds <16 x i32>, ptr %a1, i32 223 %v11 = load <16 x i32>, ptr %v10, align 6424 %v12 = tail call <16 x i32> @llvm.hexagon.V6.vmux(<64 x i1> %v6, <16 x i32> %v9, <16 x i32> %v11)25 store <16 x i32> %v12, ptr %a1, align 6426 ret <16 x i32> %v727}28 29declare <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1>, i32) #130declare <64 x i1> @llvm.hexagon.V6.pred.not(<64 x i1>) #131declare <64 x i1> @llvm.hexagon.V6.pred.scalar2(i32) #132declare <64 x i1> @llvm.hexagon.V6.pred.and(<64 x i1>, <64 x i1>) #133declare <16 x i32> @llvm.hexagon.V6.vmux(<64 x i1>, <16 x i32>, <16 x i32>) #134 35attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }36attributes #1 = { nounwind readnone }37