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1;RUN: llc -mtriple=hexagon -filetype=obj < %s -o - | llvm-objdump --no-print-imm-hex --mcpu=hexagonv60 --mattr=+hvx -d - | FileCheck %s2 3; Should not crash! and map to vxor4 5target triple = "hexagon"6 7@g0 = common global <32 x i32> zeroinitializer, align 1288 9; Function Attrs: nounwind10define i32 @f0() #0 {11b0:12 %v0 = call <32 x i32> @llvm.hexagon.V6.vd0.128B()13 store <32 x i32> %v0, ptr @g0, align 12814 ret i32 015}16; CHECK: { v{{[0-9]}} = vxor(v{{[0-9]}},v{{[0-9]}})17 18; Function Attrs: nounwind19define i32 @f1(i32 %a0) #0 {20b0:21 %v0 = alloca i8, align 122 %v1 = alloca i8, align 123 %v2 = tail call i64 @llvm.hexagon.S2.asr.i.p.rnd.goodsyntax(i64 5, i32 0)24 %v3 = trunc i64 %v2 to i825 store volatile i8 %v3, ptr %v0, align 126 %v4 = tail call i64 @llvm.hexagon.S2.asr.i.p.rnd.goodsyntax(i64 4, i32 4)27 %v5 = trunc i64 %v4 to i828 store volatile i8 %v5, ptr %v1, align 129 %v6 = load volatile i8, ptr %v0, align 130 %v7 = zext i8 %v6 to i3231 %v8 = load volatile i8, ptr %v1, align 132 %v9 = zext i8 %v8 to i3233 %v10 = add nuw nsw i32 %v9, %v734 ret i32 %v1035}36; CHECK: combine(#0,#4)37; CHECK: r{{[0-9]}}:{{[0-9]}} = asr(r{{[0-9]}}:{{[0-9]}},#3):rnd38 39; Function Attrs: nounwind readnone40declare i64 @llvm.hexagon.S2.asr.i.p.rnd.goodsyntax(i64, i32) #141 42; Function Attrs: nounwind43define i32 @f2(i32 %a0) #0 {44b0:45 %v0 = alloca i8, align 146 %v1 = alloca i8, align 147 %v2 = tail call i64 @llvm.hexagon.S5.vasrhrnd.goodsyntax(i64 6, i32 0)48 %v3 = trunc i64 %v2 to i849 store volatile i8 %v3, ptr %v0, align 150 %v4 = tail call i64 @llvm.hexagon.S5.vasrhrnd.goodsyntax(i64 4, i32 4)51 %v5 = trunc i64 %v4 to i852 store volatile i8 %v5, ptr %v0, align 153 %v6 = load volatile i8, ptr %v0, align 154 %v7 = zext i8 %v6 to i3255 %v8 = load volatile i8, ptr %v1, align 156 %v9 = zext i8 %v8 to i3257 %v10 = add nuw nsw i32 %v9, %v758 ret i32 %v1059}60; CHECK: combine(#0,#4)61; CHECK: r{{[0-9]}}:{{[0-9]}} = vasrh(r{{[0-9]}}:{{[0-9]}},#3):raw62 63; Function Attrs: nounwind readnone64declare i64 @llvm.hexagon.S5.vasrhrnd.goodsyntax(i64, i32) #165 66; Function Attrs: nounwind67define i32 @f3(i32 %a0) #0 {68b0:69 %v0 = alloca i8, align 170 %v1 = alloca i8, align 171 %v2 = tail call i32 @llvm.hexagon.S5.asrhub.rnd.sat.goodsyntax(i64 0, i32 0)72 %v3 = trunc i32 %v2 to i873 store volatile i8 %v3, ptr %v0, align 174 %v4 = tail call i32 @llvm.hexagon.S5.asrhub.rnd.sat.goodsyntax(i64 4, i32 4)75 %v5 = trunc i32 %v4 to i876 store volatile i8 %v5, ptr %v1, align 177 %v6 = load volatile i8, ptr %v0, align 178 %v7 = zext i8 %v6 to i3279 %v8 = load volatile i8, ptr %v1, align 180 %v9 = zext i8 %v8 to i3281 %v10 = add nuw nsw i32 %v9, %v782 ret i32 %v1083}84; CHECK: r{{[0-9]}} = vasrhub(r{{[0-9]}}:{{[0-9]}},#3):raw85; CHECK: r{{[0-9]}} = vsathub(r{{[0-9]}}:{{[0-9]}})86 87; Function Attrs: nounwind readnone88declare i32 @llvm.hexagon.S5.asrhub.rnd.sat.goodsyntax(i64, i32) #189 90; Function Attrs: nounwind readnone91declare <32 x i32> @llvm.hexagon.V6.vd0.128B() #192 93attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }94attributes #1 = { nounwind readnone }95