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1; RUN: llc -mtriple=hexagon -O3 < %s | FileCheck %s2; we really just want to be sure this compilation does not abort.3; CHECK: vadd4 5target triple = "hexagon"6 7@g0 = private unnamed_addr constant [39 x i8] c"\0AnumTrainingSet =%d numFeatures = %d\0A\00", align 18 9; Function Attrs: nounwind10declare i32 @f0(ptr nocapture readonly, ...) #011 12; Function Attrs: nounwind13define void @f1(ptr nocapture readnone %a0, i16 signext %a1, i16 signext %a2, ptr nocapture readnone %a3, ptr nocapture readnone %a4, ptr nocapture %a5, i16 signext %a6, i16 signext %a7) #0 {14b0:15 %v0 = sext i16 %a1 to i3216 %v1 = sext i16 %a2 to i3217 %v2 = tail call i32 (ptr, ...) @f0(ptr @g0, i32 %v0, i32 %v1) #218 %v3 = tail call <32 x i32> @llvm.hexagon.V6.vd0.128B()19 br label %b120 21b1: ; preds = %b18, %b022 %v4 = phi i32 [ 0, %b0 ], [ %v57, %b18 ]23 %v5 = phi <32 x i32> [ %v3, %b0 ], [ %v56, %b18 ]24 %v6 = icmp slt i32 %v4, %v125 br i1 %v6, label %b2, label %b326 27b2: ; preds = %b128 %v7 = tail call <32 x i32> @llvm.hexagon.V6.vasrh.128B(<32 x i32> undef, i32 16)29 %v8 = tail call <32 x i32> @llvm.hexagon.V6.vaddhsat.128B(<32 x i32> %v5, <32 x i32> %v7)30 br label %b331 32b3: ; preds = %b2, %b133 %v9 = phi <32 x i32> [ %v8, %b2 ], [ %v5, %b1 ]34 %v10 = add nuw nsw i32 %v4, 135 %v11 = icmp slt i32 %v10, %v136 br i1 %v11, label %b5, label %b637 38b4: ; preds = %b1839 %v12 = sext i16 %a6 to i3240 %v13 = tail call double @f3(double 1.000000e+00, i32 %v12) #241 %v14 = fptosi double %v13 to i3242 %v15 = mul nsw i32 %v0, 243 %v16 = sitofp i32 %v15 to double44 %v17 = tail call double @f3(double 1.000000e+00, i32 %v12) #245 %v18 = fmul double %v16, %v1746 %v19 = fptosi double %v18 to i3247 %v20 = tail call i32 @f2(i32 %v14, i32 %v19, i16 signext %a6) #248 %v21 = extractelement <32 x i32> %v56, i32 049 %v22 = mul nsw i32 %v20, %v2150 %v23 = trunc i32 %v22 to i1651 store i16 %v23, ptr %a5, align 2, !tbaa !052 ret void53 54b5: ; preds = %b355 %v24 = tail call <32 x i32> @llvm.hexagon.V6.vasrh.128B(<32 x i32> undef, i32 16)56 %v25 = tail call <32 x i32> @llvm.hexagon.V6.vaddhsat.128B(<32 x i32> %v9, <32 x i32> %v24)57 br label %b658 59b6: ; preds = %b5, %b360 %v26 = phi <32 x i32> [ %v25, %b5 ], [ %v9, %b3 ]61 %v27 = add nsw i32 %v4, 262 %v28 = icmp slt i32 %v27, %v163 br i1 %v28, label %b7, label %b864 65b7: ; preds = %b666 %v29 = tail call <32 x i32> @llvm.hexagon.V6.vasrh.128B(<32 x i32> undef, i32 16)67 %v30 = tail call <32 x i32> @llvm.hexagon.V6.vaddhsat.128B(<32 x i32> %v26, <32 x i32> %v29)68 br label %b869 70b8: ; preds = %b7, %b671 %v31 = phi <32 x i32> [ %v30, %b7 ], [ %v26, %b6 ]72 %v32 = add nsw i32 %v4, 373 %v33 = icmp slt i32 %v32, %v174 br i1 %v33, label %b9, label %b1075 76b9: ; preds = %b877 %v34 = tail call <32 x i32> @llvm.hexagon.V6.vasrh.128B(<32 x i32> undef, i32 16)78 %v35 = tail call <32 x i32> @llvm.hexagon.V6.vaddhsat.128B(<32 x i32> %v31, <32 x i32> %v34)79 br label %b1080 81b10: ; preds = %b9, %b882 %v36 = phi <32 x i32> [ %v35, %b9 ], [ %v31, %b8 ]83 %v37 = add nsw i32 %v4, 484 %v38 = icmp slt i32 %v37, %v185 br i1 %v38, label %b11, label %b1286 87b11: ; preds = %b1088 %v39 = tail call <32 x i32> @llvm.hexagon.V6.vasrh.128B(<32 x i32> undef, i32 16)89 %v40 = tail call <32 x i32> @llvm.hexagon.V6.vaddhsat.128B(<32 x i32> %v36, <32 x i32> %v39)90 br label %b1291 92b12: ; preds = %b11, %b1093 %v41 = phi <32 x i32> [ %v40, %b11 ], [ %v36, %b10 ]94 %v42 = add nsw i32 %v4, 595 %v43 = icmp slt i32 %v42, %v196 br i1 %v43, label %b13, label %b1497 98b13: ; preds = %b1299 %v44 = tail call <32 x i32> @llvm.hexagon.V6.vasrh.128B(<32 x i32> undef, i32 16)100 %v45 = tail call <32 x i32> @llvm.hexagon.V6.vaddhsat.128B(<32 x i32> %v41, <32 x i32> %v44)101 br label %b14102 103b14: ; preds = %b13, %b12104 %v46 = phi <32 x i32> [ %v45, %b13 ], [ %v41, %b12 ]105 %v47 = add nsw i32 %v4, 6106 %v48 = icmp slt i32 %v47, %v1107 br i1 %v48, label %b15, label %b16108 109b15: ; preds = %b14110 %v49 = tail call <32 x i32> @llvm.hexagon.V6.vasrh.128B(<32 x i32> undef, i32 16)111 %v50 = tail call <32 x i32> @llvm.hexagon.V6.vaddhsat.128B(<32 x i32> %v46, <32 x i32> %v49)112 br label %b16113 114b16: ; preds = %b15, %b14115 %v51 = phi <32 x i32> [ %v50, %b15 ], [ %v46, %b14 ]116 %v52 = add nsw i32 %v4, 7117 %v53 = icmp slt i32 %v52, %v1118 br i1 %v53, label %b17, label %b18119 120b17: ; preds = %b16121 %v54 = tail call <32 x i32> @llvm.hexagon.V6.vasrh.128B(<32 x i32> undef, i32 16)122 %v55 = tail call <32 x i32> @llvm.hexagon.V6.vaddhsat.128B(<32 x i32> %v51, <32 x i32> %v54)123 br label %b18124 125b18: ; preds = %b17, %b16126 %v56 = phi <32 x i32> [ %v55, %b17 ], [ %v51, %b16 ]127 %v57 = add nsw i32 %v4, 8128 %v58 = icmp eq i32 %v57, 64129 br i1 %v58, label %b4, label %b1130}131 132; Function Attrs: nounwind readnone133declare <32 x i32> @llvm.hexagon.V6.vd0.128B() #1134 135; Function Attrs: nounwind readnone136declare <32 x i32> @llvm.hexagon.V6.vasrh.128B(<32 x i32>, i32) #1137 138; Function Attrs: nounwind readnone139declare <32 x i32> @llvm.hexagon.V6.vaddhsat.128B(<32 x i32>, <32 x i32>) #1140 141declare i32 @f2(i32, i32, i16 signext) #0142 143declare double @f3(double, i32)144 145attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }146attributes #1 = { nounwind readnone }147attributes #2 = { nounwind }148 149!0 = !{!1, !1, i64 0}150!1 = !{!"short", !2, i64 0}151!2 = !{!"omnipotent char", !3, i64 0}152!3 = !{!"Simple C/C++ TBAA"}153