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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=hexagon < %s | FileCheck %s3 4; Check that we generate zero-extends, instead of just shifting and oring5; registers (which can contain sign-extended negative values).6 7define i32 @fred(i8 %a0, i8 %a1, i8 %a2, i8 %a3) #0 {8; CHECK-LABEL: fred:9; CHECK: // %bb.0: // %b410; CHECK-NEXT: {11; CHECK-NEXT: r1 = and(r1,#255)12; CHECK-NEXT: r3 = and(r3,#255)13; CHECK-NEXT: }14; CHECK-NEXT: {15; CHECK-NEXT: r0 = insert(r1,#24,#8)16; CHECK-NEXT: r2 = insert(r3,#24,#8)17; CHECK-NEXT: }18; CHECK-NEXT: {19; CHECK-NEXT: r0 = combine(r2.l,r0.l)20; CHECK-NEXT: jumpr r3121; CHECK-NEXT: }22b4:23 %v5 = insertelement <4 x i8> undef, i8 %a0, i32 024 %v6 = insertelement <4 x i8> %v5, i8 %a1, i32 125 %v7 = insertelement <4 x i8> %v6, i8 %a2, i32 226 %v8 = insertelement <4 x i8> %v7, i8 %a3, i32 327 %v9 = bitcast <4 x i8> %v8 to i3228 ret i32 %v929}30 31attributes #0 = { nounwind readnone }32