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1;RUN: llc -mtriple=hexagon < %s -o - | FileCheck %s --check-prefix=CHECK2;RUN: llc -mtriple=hexagon -mattr=+hvxv79,+hvx-length64b < %s -o - | FileCheck %s --check-prefixes=CHECK-64,CHECK-64-1283;RUN: llc -mtriple=hexagon -mattr=+hvxv79,+hvx-length128b < %s -o - | FileCheck %s --check-prefixes=CHECK-128,CHECK-64-1284 5; CHECK-LABEL: compare_vectors6; CHECK: [[REG8:(r[0-9]+):[0-9]]] = CONST64(#72340172838076673)7; CHECK: r{{[0-9]+}}:{{[0-9]+}} = and(r{{[0-9]+}}:{{[0-9]+}},[[REG8]])8; CHECK: r{{[0-9]+}}:{{[0-9]+}} = and(r{{[0-9]+}}:{{[0-9]+}},[[REG8]])9; CHECK: r{{[0-9]+}}:{{[0-9]+}} = and(r{{[0-9]+}}:{{[0-9]+}},[[REG8]])10; CHECK-128: [[REG1:(q[0-9]+)]] = vcmp.eq(v{{[0-9]+}}.b,v{{[0-9]+}}.b)11; CHECK-128: [[REG2:(r[0-9]+)]] = #-112; CHECK-128: v0 = vand([[REG1]],[[REG2]])13; CHECK-64: [[REG5:(q[0-9]+)]] = vcmp.eq(v{{[0-9]+}}.b,v{{[0-9]+}}.b)14; CHECK-64: [[REG6:(q[0-9]+)]] = vcmp.eq(v{{[0-9]+}}.b,v{{[0-9]+}}.b)15; CHECK-64: [[REG7:(r[0-9]+)]] = #-116; CHECK-64: v0 = vand([[REG5]],[[REG7]])17; CHECK-64: v1 = vand([[REG6]],[[REG7]])18define void @compare_vectors(<128 x i8> %a, <128 x i8> %b) {19entry:20 %result = icmp eq <128 x i8> %a, %b21 call i32 @f.1(<128 x i1> %result)22 ret void23}24 25; CHECK-LABEL: f.1:26; CHECK: [[REG9:(r[0-9]+)]] = and([[REG9]],##16843009)27; CHECK: [[REG10:(r[0-9]+)]] = and([[REG10]],##16843009)28; CHECK-64-128: [[REG3:(q[0-9]+)]] = vand(v0,r{{[0-9]+}})29; CHECK-64-128: [[REG4:(v[0-9]+)]] = vand([[REG3]],r{{[0-9]+}})30; CHECK-64-128: r{{[0-9]+}} = vextract([[REG4]],r{{[0-9]+}})31 32define i32 @f.1(<128 x i1> %vec){33 %element = extractelement <128 x i1> %vec, i32 634 %is_true = icmp eq i1 %element, true35 br i1 %is_true, label %if_true, label %if_false36 37if_true:38 call void @action_if_true()39 br label %end40 41if_false:42 call void @action_if_false()43 br label %end44 45end:46 %result = phi i32 [1, %if_true], [0, %if_false]47 ret i32 %result48}49 50declare void @action_if_true()51declare void @action_if_false()52