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1;RUN: llc -mtriple=hexagon < %s -o - | FileCheck %s --check-prefix=CHECK2;RUN: llc -mtriple=hexagon -mattr=+hvxv79,+hvx-length64b < %s -o - | FileCheck %s --check-prefix=CHECK-HVX3;RUN: llc -mtriple=hexagon -mattr=+hvxv79,+hvx-length128b < %s -o - | FileCheck %s --check-prefix=CHECK-HVX4 5; CHECK-LABEL: compare_vectors6; CHECK: [[REG5:(r[0-9]+):[0-9]]] = CONST64(#72340172838076673)7; CHECK: r{{[0-9]+}}:{{[0-9]+}} = and(r{{[0-9]+}}:{{[0-9]+}},[[REG5]])8; CHECK: r{{[0-9]+}}:{{[0-9]+}} = and(r{{[0-9]+}}:{{[0-9]+}},[[REG5]])9 10; CHECK-HVX: [[REG1:(q[0-9]+)]] = vcmp.eq(v{{[0-9]+}}.w,v{{[0-9]+}}.w)11; CHECK-HVX: [[REG2:(r[0-9]+)]] = #-112; CHECK-HVX: v0 = vand([[REG1]],[[REG2]])13 14define void @compare_vectors(<16 x i32> %a, <16 x i32> %b) {15entry:16 %result = icmp eq <16 x i32> %a, %b17 call i32 @f.1(<16 x i1> %result)18 ret void19}20 21; CHECK-LABEL: f.1:22; CHECK: [[REG3:(r[0-9]+)]] = and([[REG3]],##16843009)23; CHECK: [[REG4:(r[0-9]+)]] = and([[REG4]],##16843009)24; CHECK-HVX: [[REG3:(q[0-9]+)]] = vand(v0,r{{[0-9]+}})25; CHECK-HVX: [[REG4:(v[0-9]+)]] = vand([[REG3]],r{{[0-9]+}})26; CHECK-HVX: r{{[0-9]+}} = vextract([[REG4]],r{{[0-9]+}})27 28define i32 @f.1(<16 x i1> %vec) {29 %element = extractelement <16 x i1> %vec, i32 630 %is_true = icmp eq i1 %element, true31 br i1 %is_true, label %if_true, label %if_false32 33if_true:34 call void @action_if_true()35 br label %end36 37if_false:38 call void @action_if_false()39 br label %end40 41end:42 %result = phi i32 [1, %if_true], [0, %if_false]43 ret i32 %result44}45 46declare void @action_if_true()47declare void @action_if_false()48