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1; RUN: llc -mtriple=hexagon -verify-machineinstrs=true < %s | FileCheck %s2; Testing for these 5 variants of circular store:3; Q6_circ_store_update_B(inputLR, pDelay, -1, nConvLength, 4);4; Q6_circ_store_update_D(inputLR, pDelay, -1, nConvLength, 4);5; Q6_circ_store_update_HL(inputLR, pDelay, -1, nConvLength, 4);6; Q6_circ_store_update_HH(inputLR, pDelay, -1, nConvLength, 4);7; Q6_circ_store_update_W(inputLR, pDelay, -1, nConvLength, 4);8; producing these9; memb(r1++#-1:circ(m0)) = r310; memd(r1++#-8:circ(m0)) = r1:011; memh(r1++#-2:circ(m0)) = r312; memh(r1++#-2:circ(m0)) = r3.h13; memw(r1++#-4:circ(m0)) = r014 15target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32"16target triple = "hexagon"17 18define zeroext i8 @foo1(i16 zeroext %filtMemLen, ptr %filtMemLR, i16 signext %filtMemIndex) nounwind {19entry:20 %conv = zext i16 %filtMemLen to i3221 %shr2 = lshr i32 %conv, 122 %idxprom = sext i16 %filtMemIndex to i3223 %arrayidx = getelementptr inbounds i16, ptr %filtMemLR, i32 %idxprom24 %or = or i32 %shr2, 3355443225; CHECK: memb(r{{[0-9]+}}++#-1:circ(m{{[0-1]}}))26 %0 = tail call ptr @llvm.hexagon.circ.stb(ptr %arrayidx, i32 0, i32 %or, i32 -1)27 ret i8 028}29 30declare ptr @llvm.hexagon.circ.stb(ptr, i32, i32, i32) nounwind31 32define i64 @foo2(i16 zeroext %filtMemLen, ptr %filtMemLR, i16 signext %filtMemIndex) nounwind {33entry:34 %conv = zext i16 %filtMemLen to i3235 %shr1 = lshr i32 %conv, 136 %idxprom = sext i16 %filtMemIndex to i3237 %arrayidx = getelementptr inbounds i16, ptr %filtMemLR, i32 %idxprom38 %shl = shl nuw nsw i32 %shr1, 339 %or = or i32 %shl, 8388608040; CHECK: memd(r{{[0-9]+}}++#-8:circ(m{{[0-1]}}))41 %0 = tail call ptr @llvm.hexagon.circ.std(ptr %arrayidx, i64 undef, i32 %or, i32 -8)42 ret i64 043}44 45declare ptr @llvm.hexagon.circ.std(ptr, i64, i32, i32) nounwind46 47define signext i16 @foo3(i16 zeroext %filtMemLen, ptr %filtMemLR, i16 signext %filtMemIndex) nounwind {48entry:49 %conv = zext i16 %filtMemLen to i3250 %shr2 = and i32 %conv, 6553451 %idxprom = sext i16 %filtMemIndex to i3252 %arrayidx = getelementptr inbounds i16, ptr %filtMemLR, i32 %idxprom53 %or = or i32 %shr2, 5033164854; CHECK: memh(r{{[0-9]+}}++#-2:circ(m{{[0-1]}}))55 %0 = tail call ptr @llvm.hexagon.circ.sth(ptr %arrayidx, i32 0, i32 %or, i32 -2)56 ret i16 057}58 59declare ptr @llvm.hexagon.circ.sth(ptr, i32, i32, i32) nounwind60 61define signext i16 @foo5(i16 zeroext %filtMemLen, ptr %filtMemLR, i16 signext %filtMemIndex) nounwind {62entry:63 %conv = zext i16 %filtMemLen to i3264 %shr2 = and i32 %conv, 6553465 %idxprom = sext i16 %filtMemIndex to i3266 %arrayidx = getelementptr inbounds i16, ptr %filtMemLR, i32 %idxprom67 %or = or i32 %shr2, 5033164868; CHECK: memh(r{{[0-9]+}}++#-2:circ(m{{[0-1]}})) = r{{[0-9]*}}.h69 %0 = tail call ptr @llvm.hexagon.circ.sthhi(ptr %arrayidx, i32 0, i32 %or, i32 -2)70 ret i16 071}72 73declare ptr @llvm.hexagon.circ.sthhi(ptr, i32, i32, i32) nounwind74 75define i32 @foo6(i16 zeroext %filtMemLen, ptr %filtMemLR, i16 signext %filtMemIndex) nounwind {76entry:77 %conv = zext i16 %filtMemLen to i3278 %shr1 = lshr i32 %conv, 179 %idxprom = sext i16 %filtMemIndex to i3280 %arrayidx = getelementptr inbounds i16, ptr %filtMemLR, i32 %idxprom81 %shl = shl nuw nsw i32 %shr1, 282 %or = or i32 %shl, 6710886483; CHECK: memw(r{{[0-9]+}}++#-4:circ(m{{[0-1]}}))84 %0 = tail call ptr @llvm.hexagon.circ.stw(ptr %arrayidx, i32 undef, i32 %or, i32 -4)85 ret i32 086}87 88declare ptr @llvm.hexagon.circ.stw(ptr, i32, i32, i32) nounwind89 90!0 = !{!"omnipotent char", !1}91!1 = !{!"Simple C/C++ TBAA"}92!2 = !{!"short", !0}93!3 = !{!"int", !0}94