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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=hexagon -hexagon-bit=0 < %s | FileCheck %s3; Optimized bitwise operations.4 5define i32 @my_clrbit(i32 %x) nounwind {6; CHECK-LABEL: my_clrbit:7; CHECK: // %bb.0: // %entry8; CHECK-NEXT: {9; CHECK-NEXT: r0 = clrbit(r0,#31)10; CHECK-NEXT: r1 = r011; CHECK-NEXT: r29 = add(r29,#-8)12; CHECK-NEXT: }13; CHECK-NEXT: {14; CHECK-NEXT: r29 = add(r29,#8)15; CHECK-NEXT: jumpr r3116; CHECK-NEXT: memw(r29+#4) = r117; CHECK-NEXT: }18entry:19 %x.addr = alloca i32, align 420 store i32 %x, ptr %x.addr, align 421 %0 = load i32, ptr %x.addr, align 422 %and = and i32 %0, 214748364723 ret i32 %and24}25 26define i64 @my_clrbit2(i64 %x) nounwind {27; CHECK-LABEL: my_clrbit2:28; CHECK: // %bb.0: // %entry29; CHECK-NEXT: {30; CHECK-NEXT: r29 = add(r29,#-8)31; CHECK-NEXT: }32; CHECK-NEXT: {33; CHECK-NEXT: r0 = clrbit(r0,#31)34; CHECK-NEXT: jumpr r3135; CHECK-NEXT: r29 = add(r29,#8)36; CHECK-NEXT: memd(r29+#0) = r1:037; CHECK-NEXT: }38entry:39 %x.addr = alloca i64, align 840 store i64 %x, ptr %x.addr, align 841 %0 = load i64, ptr %x.addr, align 842 %and = and i64 %0, -214748364943 ret i64 %and44}45 46define i64 @my_clrbit3(i64 %x) nounwind {47; CHECK-LABEL: my_clrbit3:48; CHECK: // %bb.0: // %entry49; CHECK-NEXT: {50; CHECK-NEXT: r29 = add(r29,#-8)51; CHECK-NEXT: }52; CHECK-NEXT: {53; CHECK-NEXT: r1 = clrbit(r1,#31)54; CHECK-NEXT: jumpr r3155; CHECK-NEXT: r29 = add(r29,#8)56; CHECK-NEXT: memd(r29+#0) = r1:057; CHECK-NEXT: }58entry:59 %x.addr = alloca i64, align 860 store i64 %x, ptr %x.addr, align 861 %0 = load i64, ptr %x.addr, align 862 %and = and i64 %0, 922337203685477580763 ret i64 %and64}65 66define i32 @my_clrbit4(i32 %x) nounwind {67; CHECK-LABEL: my_clrbit4:68; CHECK: // %bb.0: // %entry69; CHECK-NEXT: {70; CHECK-NEXT: r0 = clrbit(r0,#13)71; CHECK-NEXT: r1 = r072; CHECK-NEXT: r29 = add(r29,#-8)73; CHECK-NEXT: }74; CHECK-NEXT: {75; CHECK-NEXT: r29 = add(r29,#8)76; CHECK-NEXT: jumpr r3177; CHECK-NEXT: memw(r29+#4) = r178; CHECK-NEXT: }79entry:80 %x.addr = alloca i32, align 481 store i32 %x, ptr %x.addr, align 482 %0 = load i32, ptr %x.addr, align 483 %and = and i32 %0, -819384 ret i32 %and85}86 87define i64 @my_clrbit5(i64 %x) nounwind {88; CHECK-LABEL: my_clrbit5:89; CHECK: // %bb.0: // %entry90; CHECK-NEXT: {91; CHECK-NEXT: r29 = add(r29,#-8)92; CHECK-NEXT: }93; CHECK-NEXT: {94; CHECK-NEXT: r0 = clrbit(r0,#13)95; CHECK-NEXT: jumpr r3196; CHECK-NEXT: r29 = add(r29,#8)97; CHECK-NEXT: memd(r29+#0) = r1:098; CHECK-NEXT: }99entry:100 %x.addr = alloca i64, align 8101 store i64 %x, ptr %x.addr, align 8102 %0 = load i64, ptr %x.addr, align 8103 %and = and i64 %0, -8193104 ret i64 %and105}106 107define i64 @my_clrbit6(i64 %x) nounwind {108; CHECK-LABEL: my_clrbit6:109; CHECK: // %bb.0: // %entry110; CHECK-NEXT: {111; CHECK-NEXT: r29 = add(r29,#-8)112; CHECK-NEXT: }113; CHECK-NEXT: {114; CHECK-NEXT: r1 = clrbit(r1,#27)115; CHECK-NEXT: jumpr r31116; CHECK-NEXT: r29 = add(r29,#8)117; CHECK-NEXT: memd(r29+#0) = r1:0118; CHECK-NEXT: }119entry:120 %x.addr = alloca i64, align 8121 store i64 %x, ptr %x.addr, align 8122 %0 = load i64, ptr %x.addr, align 8123 %and = and i64 %0, -576460752303423489124 ret i64 %and125}126 127define zeroext i16 @my_setbit(i16 zeroext %crc) nounwind {128; CHECK-LABEL: my_setbit:129; CHECK: // %bb.0: // %entry130; CHECK-NEXT: {131; CHECK-NEXT: r0 = setbit(r0,#15)132; CHECK-NEXT: r29 = add(r29,#-8)133; CHECK-NEXT: }134; CHECK-NEXT: {135; CHECK-NEXT: r29 = add(r29,#8)136; CHECK-NEXT: jumpr r31137; CHECK-NEXT: memh(r29+#6) = r0138; CHECK-NEXT: }139entry:140 %crc.addr = alloca i16, align 2141 store i16 %crc, ptr %crc.addr, align 2142 %0 = load i16, ptr %crc.addr, align 2143 %conv = zext i16 %0 to i32144 %or = or i32 %conv, 32768145 %conv1 = trunc i32 %or to i16146 store i16 %conv1, ptr %crc.addr, align 2147 %1 = load i16, ptr %crc.addr, align 2148 ret i16 %1149}150 151define i32 @my_setbit2(i32 %x) nounwind {152; CHECK-LABEL: my_setbit2:153; CHECK: // %bb.0: // %entry154; CHECK-NEXT: {155; CHECK-NEXT: r0 = setbit(r0,#15)156; CHECK-NEXT: r1 = r0157; CHECK-NEXT: r29 = add(r29,#-8)158; CHECK-NEXT: }159; CHECK-NEXT: {160; CHECK-NEXT: r29 = add(r29,#8)161; CHECK-NEXT: jumpr r31162; CHECK-NEXT: memw(r29+#4) = r1163; CHECK-NEXT: }164entry:165 %x.addr = alloca i32, align 4166 store i32 %x, ptr %x.addr, align 4167 %0 = load i32, ptr %x.addr, align 4168 %or = or i32 %0, 32768169 ret i32 %or170}171 172define i64 @my_setbit3(i64 %x) nounwind {173; CHECK-LABEL: my_setbit3:174; CHECK: // %bb.0: // %entry175; CHECK-NEXT: {176; CHECK-NEXT: r29 = add(r29,#-8)177; CHECK-NEXT: }178; CHECK-NEXT: {179; CHECK-NEXT: r0 = setbit(r0,#15)180; CHECK-NEXT: jumpr r31181; CHECK-NEXT: r29 = add(r29,#8)182; CHECK-NEXT: memd(r29+#0) = r1:0183; CHECK-NEXT: }184entry:185 %x.addr = alloca i64, align 8186 store i64 %x, ptr %x.addr, align 8187 %0 = load i64, ptr %x.addr, align 8188 %or = or i64 %0, 32768189 ret i64 %or190}191 192define i32 @my_setbit4(i32 %x) nounwind {193; CHECK-LABEL: my_setbit4:194; CHECK: // %bb.0: // %entry195; CHECK-NEXT: {196; CHECK-NEXT: r0 = setbit(r0,#31)197; CHECK-NEXT: r1 = r0198; CHECK-NEXT: r29 = add(r29,#-8)199; CHECK-NEXT: }200; CHECK-NEXT: {201; CHECK-NEXT: r29 = add(r29,#8)202; CHECK-NEXT: jumpr r31203; CHECK-NEXT: memw(r29+#4) = r1204; CHECK-NEXT: }205entry:206 %x.addr = alloca i32, align 4207 store i32 %x, ptr %x.addr, align 4208 %0 = load i32, ptr %x.addr, align 4209 %or = or i32 %0, -2147483648210 ret i32 %or211}212 213define i64 @my_setbit5(i64 %x) nounwind {214; CHECK-LABEL: my_setbit5:215; CHECK: // %bb.0: // %entry216; CHECK-NEXT: {217; CHECK-NEXT: r29 = add(r29,#-8)218; CHECK-NEXT: }219; CHECK-NEXT: {220; CHECK-NEXT: r1 = setbit(r1,#13)221; CHECK-NEXT: jumpr r31222; CHECK-NEXT: r29 = add(r29,#8)223; CHECK-NEXT: memd(r29+#0) = r1:0224; CHECK-NEXT: }225entry:226 %x.addr = alloca i64, align 8227 store i64 %x, ptr %x.addr, align 8228 %0 = load i64, ptr %x.addr, align 8229 %or = or i64 %0, 35184372088832230 ret i64 %or231}232 233define zeroext i16 @my_togglebit(i16 zeroext %crc) nounwind {234; CHECK-LABEL: my_togglebit:235; CHECK: // %bb.0: // %entry236; CHECK-NEXT: {237; CHECK-NEXT: r0 = togglebit(r0,#15)238; CHECK-NEXT: r29 = add(r29,#-8)239; CHECK-NEXT: }240; CHECK-NEXT: {241; CHECK-NEXT: r29 = add(r29,#8)242; CHECK-NEXT: jumpr r31243; CHECK-NEXT: memh(r29+#6) = r0244; CHECK-NEXT: }245entry:246 %crc.addr = alloca i16, align 2247 store i16 %crc, ptr %crc.addr, align 2248 %0 = load i16, ptr %crc.addr, align 2249 %conv = zext i16 %0 to i32250 %xor = xor i32 %conv, 32768251 %conv1 = trunc i32 %xor to i16252 store i16 %conv1, ptr %crc.addr, align 2253 %1 = load i16, ptr %crc.addr, align 2254 ret i16 %1255}256 257define i32 @my_togglebit2(i32 %x) nounwind {258; CHECK-LABEL: my_togglebit2:259; CHECK: // %bb.0: // %entry260; CHECK-NEXT: {261; CHECK-NEXT: r0 = togglebit(r0,#15)262; CHECK-NEXT: r1 = r0263; CHECK-NEXT: r29 = add(r29,#-8)264; CHECK-NEXT: }265; CHECK-NEXT: {266; CHECK-NEXT: r29 = add(r29,#8)267; CHECK-NEXT: jumpr r31268; CHECK-NEXT: memw(r29+#4) = r1269; CHECK-NEXT: }270entry:271 %x.addr = alloca i32, align 4272 store i32 %x, ptr %x.addr, align 4273 %0 = load i32, ptr %x.addr, align 4274 %xor = xor i32 %0, 32768275 ret i32 %xor276}277 278define i64 @my_togglebit3(i64 %x) nounwind {279; CHECK-LABEL: my_togglebit3:280; CHECK: // %bb.0: // %entry281; CHECK-NEXT: {282; CHECK-NEXT: r29 = add(r29,#-8)283; CHECK-NEXT: }284; CHECK-NEXT: {285; CHECK-NEXT: r0 = togglebit(r0,#15)286; CHECK-NEXT: jumpr r31287; CHECK-NEXT: r29 = add(r29,#8)288; CHECK-NEXT: memd(r29+#0) = r1:0289; CHECK-NEXT: }290entry:291 %x.addr = alloca i64, align 8292 store i64 %x, ptr %x.addr, align 8293 %0 = load i64, ptr %x.addr, align 8294 %xor = xor i64 %0, 32768295 ret i64 %xor296}297 298define i64 @my_togglebit4(i64 %x) nounwind {299; CHECK-LABEL: my_togglebit4:300; CHECK: // %bb.0: // %entry301; CHECK-NEXT: {302; CHECK-NEXT: r29 = add(r29,#-8)303; CHECK-NEXT: }304; CHECK-NEXT: {305; CHECK-NEXT: r1 = togglebit(r1,#20)306; CHECK-NEXT: jumpr r31307; CHECK-NEXT: r29 = add(r29,#8)308; CHECK-NEXT: memd(r29+#0) = r1:0309; CHECK-NEXT: }310entry:311 %x.addr = alloca i64, align 8312 store i64 %x, ptr %x.addr, align 8313 %0 = load i64, ptr %x.addr, align 8314 %xor = xor i64 %0, 4503599627370496315 ret i64 %xor316}317