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1; RUN: llc -mtriple=hexagon < %s | FileCheck %s2 3target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"4target triple = "hexagon"5 6; Check that this code only spills a single vector.7; CHECK-NOT: vmem(#r29+{{[^0]}})8 9%struct.descr = type opaque10 11define inreg <64 x i32> @danny(ptr %desc, i32 %xy0, i32 %xy1) #0 {12entry:13 %call = tail call inreg <32 x i32> @sammy(ptr %desc, i32 %xy0) #314 %call1 = tail call inreg <32 x i32> @kirby(ptr %desc, i32 %xy1) #315 %0 = tail call <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32> %call1, <32 x i32> %call)16 ret <64 x i32> %017}18 19declare inreg <32 x i32> @sammy(ptr, i32) #120declare inreg <32 x i32> @kirby(ptr, i32) #121declare <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32>, <32 x i32>) #222 23attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-length128b,+hvxv60" }24attributes #1 = { "target-cpu"="hexagonv60" "target-features"="+hvx-length128b,+hvxv60" }25attributes #2 = { nounwind readnone }26attributes #3 = { nounwind }27