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1; RUN: llc -mtriple=hexagon -O2 < %s | FileCheck %s2 3; In DAG combiner, eliminate a store in cases where the store is fed by a4; load from the same location. This is already done in cases where the store's5; chain reaches the "output chain" of the load, this tests for cases where6; the load's "input chain" is reached via an intervening node (eg. TokenFactor)7; that ensures ordering.8 9target triple = "hexagon"10 11%s.0 = type { [3 x i32] }12 13; Function Attrs: nounwind14define void @f0(i32 %a0, i32 %a1, ptr nocapture %a2, ptr nocapture %a3) #0 {15b0:16; Pick one store that happens as a result. This isn't the best, but a regular17; expression for a register name matches some unrelated load.18; CHECK: %bb.19; CHECK: = memw(r3+#8)20; CHECK-NOT: memw(r3+#8) =21; CHECK: %bb.22 call void @llvm.memcpy.p0.p0.i32(ptr align 4 %a2, ptr align 4 %a3, i32 12, i1 false)23 %v3 = zext i32 %a0 to i9624 %v4 = load i96, ptr %a2, align 425 %v5 = shl nuw nsw i96 %v3, 4826 %v6 = and i96 %v5, 28147497671065627 %v7 = and i96 %v4, -28147497671065728 %v8 = or i96 %v7, %v629 store i96 %v8, ptr %a2, align 430 %v9 = icmp eq i32 %a1, 214748364731 br i1 %v9, label %b1, label %b232 33b1: ; preds = %b034 %v10 = and i96 %v8, -1258291335 br label %b336 37b2: ; preds = %b038 %v12 = load i96, ptr %a3, align 439 %v13 = trunc i96 %v12 to i3240 %v14 = add i32 %v13, %a141 %v15 = zext i32 %v14 to i9642 %v16 = and i96 %v15, 419430343 %v17 = and i96 %v8, -419430444 %v18 = or i96 %v16, %v1745 store i96 %v18, ptr %a2, align 446 %v19 = load i96, ptr %a3, align 447 %v20 = and i96 %v19, 1258291248 %v21 = and i96 %v18, -1258291349 %v22 = or i96 %v21, %v2050 br label %b351 52b3: ; preds = %b2, %b153 %v23 = phi i96 [ %v22, %b2 ], [ %v10, %b1 ]54 store i96 %v23, ptr %a2, align 455 ret void56}57 58; Function Attrs: argmemonly nounwind59declare void @llvm.memcpy.p0.p0.i32(ptr nocapture writeonly, ptr nocapture readonly, i32, i1) #160 61attributes #0 = { nounwind }62attributes #1 = { argmemonly nounwind }63