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1; RUN: llc -mtriple=hexagon < %s 2>&1 | FileCheck %s2 3; Generating a compound instruction with a constant is not profitable.4; The constant needs to be kept in a register before it is fed to compound5; instruction.6; Before, we are generating7; ra = #65820;8; rb = lsr(rb, #8);9; rc ^= and (rb, ra)10; Now, we are generating11; ra = and (#65820, lsr(ra, #8));12; rb = xor(rb, ra)13 14; CHECK: and(##65280,lsr(r15; CHECK-NOT: ^= and16 17define dso_local zeroext i16 @test_compound(i16 zeroext %varA, i16 zeroext %varB) local_unnamed_addr #0 {18entry:19 %tmp = zext i16 %varB to i3220 %tmp1 = and i16 %varA, 25521 %tmp2 = zext i16 %tmp1 to i3222 %.masked.i = and i32 %tmp, 25523 %tmp3 = xor i32 %.masked.i, %tmp224 %tmp4 = tail call i64 @llvm.hexagon.M4.pmpyw(i32 %tmp3, i32 255) #225 %tmp5 = trunc i64 %tmp4 to i3226 %tmp6 = and i32 %tmp5, 25527 %tmp7 = tail call i64 @llvm.hexagon.M4.pmpyw(i32 %tmp6, i32 81922) #228 %tmp8 = trunc i64 %tmp7 to i3229 %tmp9 = xor i32 %tmp8, %tmp30 %tmp10 = lshr i32 %tmp9, 831 %tmp11 = lshr i16 %varA, 832 %conv2 = zext i16 %tmp11 to i3233 %tmp12 = and i32 %tmp10, 6528034 %.masked.i7 = and i32 %tmp10, 25535 %tmp13 = xor i32 %.masked.i7, %conv236 %tmp14 = tail call i64 @llvm.hexagon.M4.pmpyw(i32 %tmp13, i32 255) #237 %tmp15 = trunc i64 %tmp14 to i3238 %tmp16 = and i32 %tmp15, 25539 %tmp17 = tail call i64 @llvm.hexagon.M4.pmpyw(i32 %tmp16, i32 81922) #240 %tmp18 = trunc i64 %tmp17 to i3241 %tmp19 = xor i32 %tmp12, %tmp1842 %tmp20 = lshr i32 %tmp19, 843 %tmp21 = trunc i32 %tmp20 to i1644 ret i16 %tmp2145}46 47; Function Attrs: nounwind readnone48declare i64 @llvm.hexagon.M4.pmpyw(i32, i32) #149 50attributes #0 = { nounwind readnone "target-cpu"="hexagonv65" }51attributes #1 = { nounwind readnone }52attributes #2 = { nounwind }53