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1; RUN: llc -mtriple=hexagon -mcpu=hexagonv55 -filetype=obj -o /dev/null2; REQUIRES: asserts3; There should be no output (nothing on stderr).4 5; Due to a bug in converting a dot-new branch into a dot-old one, opcodes6; with branch prediction bits were selected even if the architecture did7; not support them. On V55-, the dot-old branch opcodes are J2_jumpt and8; J2_jumpf (and a pair of J2_jumpr*), whereas J2_jumptpt could have been9; a result of the conversion to dot-old. This would fail a verification10; check in the MC code emitter, so make sure it does not happen.11 12target triple = "hexagon"13 14define void @fred(ptr nocapture %a0, ptr nocapture %a1, ptr nocapture %a2, i16 signext %a3, ptr %a4, i16 signext %a5, i16 signext %a6, i16 signext %a7, i32 %a8, i16 signext %a9, i16 signext %a10) local_unnamed_addr #0 {15b11:16 %v12 = sext i16 %a5 to i3217 %v13 = tail call i32 @llvm.hexagon.A2.sxth(i32 %v12)18 %v14 = tail call i32 @llvm.hexagon.A2.sxth(i32 2)19 %v15 = tail call i32 @llvm.hexagon.A2.sxth(i32 undef)20 %v16 = tail call i32 @llvm.hexagon.A2.sath(i32 undef)21 %v17 = tail call i32 @llvm.hexagon.A2.sxth(i32 %v16)22 %v18 = tail call i32 @llvm.hexagon.A2.aslh(i32 undef)23 %v19 = tail call i32 @llvm.hexagon.S2.asr.r.r.sat(i32 %v18, i32 %v14)24 %v20 = tail call i32 @llvm.hexagon.A2.asrh(i32 %v19)25 %v21 = tail call i32 @llvm.hexagon.A2.sxth(i32 %v20)26 %v22 = tail call i32 @llvm.hexagon.A2.sub(i32 %v17, i32 %v21)27 %v23 = tail call i32 @llvm.hexagon.A2.sath(i32 %v22)28 %v24 = select i1 undef, i32 undef, i32 %v2329 %v25 = tail call i32 @llvm.hexagon.A2.sxth(i32 %v24)30 %v26 = tail call i32 @llvm.hexagon.A2.sub(i32 %v13, i32 %v25)31 %v27 = tail call i32 @llvm.hexagon.A2.sath(i32 %v26)32 %v28 = tail call i32 @llvm.hexagon.A2.sxth(i32 %v27)33 %v29 = tail call i32 @llvm.hexagon.A2.sub(i32 %v28, i32 %v14)34 %v30 = tail call i32 @llvm.hexagon.A2.sath(i32 %v29)35 %v31 = shl i32 %v30, 1636 %v32 = icmp sgt i32 undef, %v3137 %v33 = select i1 %v32, i32 %v30, i32 undef38 %v34 = trunc i32 %v33 to i1639 %v35 = trunc i32 %v24 to i1640 call void @foo(ptr nonnull undef, ptr nonnull undef, ptr %a4, i16 signext %v35, i16 signext %v34, i16 signext 2) #441 %v36 = call i32 @llvm.hexagon.S2.asr.r.r.sat(i32 %v18, i32 undef)42 %v37 = call i32 @llvm.hexagon.A2.asrh(i32 %v36)43 %v38 = call i32 @llvm.hexagon.A2.sub(i32 %v13, i32 undef)44 %v39 = call i32 @llvm.hexagon.A2.sath(i32 %v38)45 %v40 = call i32 @llvm.hexagon.A2.sxth(i32 %v39)46 %v41 = call i32 @llvm.hexagon.A2.sub(i32 %v40, i32 %v14)47 %v42 = call i32 @llvm.hexagon.A2.sath(i32 %v41)48 %v43 = select i1 undef, i32 %v42, i32 %v3749 %v44 = trunc i32 %v43 to i1650 call void @foo(ptr nonnull undef, ptr nonnull undef, ptr %a4, i16 signext undef, i16 signext %v44, i16 signext 2) #451 %v45 = call i32 @llvm.hexagon.A2.sath(i32 undef)52 %v46 = select i1 undef, i32 undef, i32 %v4553 %v47 = trunc i32 %v46 to i1654 call void @foo(ptr nonnull undef, ptr nonnull undef, ptr %a4, i16 signext %v47, i16 signext undef, i16 signext 2) #455 %v48 = call i32 @llvm.hexagon.A2.sub(i32 undef, i32 %v15)56 %v49 = call i32 @llvm.hexagon.A2.sath(i32 %v48)57 %v50 = trunc i32 %v49 to i1658 store i16 %v50, ptr undef, align 259 store i16 %a3, ptr %a0, align 260 %v51 = sext i16 %a10 to i3261 %v52 = call i32 @llvm.hexagon.A2.sxth(i32 %v51)62 %v53 = call i32 @llvm.hexagon.A2.add(i32 undef, i32 %v52)63 %v54 = call i32 @llvm.hexagon.A2.sath(i32 %v53)64 %v55 = trunc i32 %v54 to i1665 store i16 %v55, ptr %a1, align 266 store i16 %a7, ptr %a2, align 267 %v56 = sext i16 %a9 to i3268 %v57 = call i32 @llvm.hexagon.A2.sxth(i32 %v56)69 br i1 undef, label %b58, label %b6270 71b58: ; preds = %b1172 %v59 = call i32 @llvm.hexagon.A2.add(i32 %v57, i32 %v52)73 %v60 = call i32 @llvm.hexagon.A2.sath(i32 %v59)74 %v61 = trunc i32 %v60 to i1675 store i16 %v61, ptr %a1, align 276 br label %b6377 78b62: ; preds = %b1179 br label %b6380 81b63: ; preds = %b62, %b5882 %v64 = phi i16 [ undef, %b58 ], [ %a9, %b62 ]83 %v65 = icmp slt i16 undef, %v6484 br i1 %v65, label %b66, label %b6785 86b66: ; preds = %b6387 br i1 undef, label %b67, label %b6888 89b67: ; preds = %b66, %b6390 store i16 0, ptr %a2, align 291 br label %b6892 93b68: ; preds = %b67, %b6694 ret void95}96 97declare i32 @llvm.hexagon.A2.sath(i32) #298declare i32 @llvm.hexagon.A2.add(i32, i32) #299declare i32 @llvm.hexagon.A2.sxth(i32) #2100declare i32 @llvm.hexagon.A2.sub(i32, i32) #2101declare i32 @llvm.hexagon.A2.asrh(i32) #2102declare i32 @llvm.hexagon.S2.asr.r.r.sat(i32, i32) #2103declare i32 @llvm.hexagon.A2.aslh(i32) #2104declare void @foo(ptr, ptr, ptr, i16 signext, i16 signext, i16 signext) local_unnamed_addr #3105 106attributes #0 = { nounwind optsize "target-cpu"="hexagonv55" "target-features"="-hvx,-long-calls" }107attributes #1 = { argmemonly nounwind }108attributes #2 = { nounwind readnone }109attributes #3 = { optsize "target-cpu"="hexagonv55" "target-features"="-hvx,-long-calls" }110attributes #4 = { nounwind optsize }111