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1; RUN: llc -mtriple=hexagon < %s2; REQUIRES: asserts3 4; Test that the DAG combiner doesn't assert because it attempts to replace5; the chain of a post-increment store based upon alias information. The code6; in DAGCombiner is unable to convert indexed stores.7 8; Function Attrs: nounwind9define void @f0(i32 %a0, ptr %a1, ptr %a2) #0 {10b0:11 switch i32 %a0, label %b5 [12 i32 67830273, label %b113 i32 67502595, label %b314 ]15 16b1: ; preds = %b017 br i1 undef, label %b2, label %b518 19b2: ; preds = %b120 br label %b521 22b3: ; preds = %b023 br i1 undef, label %b4, label %b524 25b4: ; preds = %b326 store i32 0, ptr %a2, align 1, !tbaa !027 %v1 = getelementptr inbounds i8, ptr %a1, i32 428 %v3 = load i32, ptr %v1, align 4, !tbaa !529 %v4 = getelementptr inbounds i8, ptr %a2, i32 430 store i32 %v3, ptr %v4, align 1, !tbaa !531 br label %b532 33b5: ; preds = %b4, %b3, %b2, %b1, %b034 ret void35}36 37attributes #0 = { nounwind "target-cpu"="hexagonv55" }38 39!0 = !{!1, !2, i64 0}40!1 = !{!"", !2, i64 0, !2, i64 4}41!2 = !{!"long", !3, i64 0}42!3 = !{!"omnipotent char", !4, i64 0}43!4 = !{!"Simple C/C++ TBAA"}44!5 = !{!1, !2, i64 4}45