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1; RUN: llc -mtriple=hexagon < %s2; REQUIRES: asserts3 4; The register coalescer created (via rematerialization) a definition of5; a register (R0), which had "undef" flag set. This caused the def to be6; ignored in the dependence graph, which then lead to an invalid instruction7; move in the machine scheduler (and an assert).8; The undef flags are already being cleared in the register cleanup, but9; that happens after register allocation. The undef flags need to be cleared10; earlier to avoid this issue.11 12%0 = type <{ ptr, ptr, i16, i8, i8, i8 }>13%1 = type { %2, %5, [3 x %3] }14%2 = type { %3, %4, i16, i16 }15%3 = type { i32, i32, i8, i8 }16%4 = type { i32, i32, i32 }17%5 = type { i8, i8, i8, i8, i32, i32, i16, i16, i32, i8, i8, i8, i32, i32, i16, i16, i32 }18%6 = type { %7, i8, i16, i16, i8, i8, i8, i8, i8 }19%7 = type { i32, i32, i16, i16, i16, i8 }20 21@g0 = external constant %0, align 122 23; Function Attrs: nounwind readnone24declare i32 @llvm.hexagon.M2.mpy.up(i32, i32) #125 26declare void @f0(ptr, i32, i32, i32, i32, i32)27 28define void @f1(i8 zeroext %a0, ptr nocapture %a1, i8 zeroext %a2, i8 zeroext %a3) #0 {29b0:30 %v0 = getelementptr inbounds %1, ptr %a1, i32 0, i32 1, i32 931 %v1 = load i8, ptr %v0, align 132 %v2 = zext i8 %v1 to i3233 %v3 = getelementptr inbounds %1, ptr %a1, i32 0, i32 2, i32 %v234 %v4 = tail call ptr @f2(i32 undef, i8 zeroext 0)35 br i1 undef, label %b1, label %b536 37b1: ; preds = %b038 %v5 = tail call i32 @llvm.hexagon.M2.mpy.up(i32 undef, i32 undef)39 %v6 = tail call i32 @llvm.hexagon.M2.mpy.up(i32 undef, i32 undef)40 %v7 = zext i32 %v5 to i6441 %v8 = zext i32 %v6 to i6442 %v9 = add nuw nsw i64 %v8, %v743 %v10 = lshr i64 %v9, 544 %v11 = trunc i64 %v10 to i3245 store i32 %v11, ptr undef, align 446 br i1 undef, label %b3, label %b247 48b2: ; preds = %b149 store i32 0, ptr %v3, align 450 tail call void @f0(ptr @g0, i32 undef, i32 0, i32 undef, i32 undef, i32 undef)51 br label %b452 53b3: ; preds = %b154 br label %b455 56b4: ; preds = %b3, %b257 unreachable58 59b5: ; preds = %b060 br i1 undef, label %b6, label %b761 62b6: ; preds = %b563 unreachable64 65b7: ; preds = %b566 unreachable67}68 69declare ptr @f2(i32, i8 zeroext)70 71attributes #0 = { nounwind "target-cpu"="hexagonv55" }72attributes #1 = { nounwind readnone }73