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1; RUN: llc -mtriple=hexagon < %s | FileCheck %s2; Make sure that the loop in the end has only one basic block.3 4; CHECK-LABEL: fred5; CHECK: %b26; Rely on the comments, make sure the one for the loop header is present.7; CHECK: %loop8; CHECK: %should_merge9; CHECK: %exit10 11target triple = "hexagon"12 13define i32 @fred(i32 %a0, ptr nocapture readonly %a1) #0 {14b2:15 %v4 = getelementptr inbounds i32, ptr %a1, i32 116 %v5 = zext i32 %a0 to i6417 br label %loop18 19loop: ; preds = %should_merge, %b220 %v7 = phi i32 [ 0, %b2 ], [ %v49, %should_merge ]21 %v8 = phi i32 [ 0, %b2 ], [ %v42, %should_merge ]22 %v9 = phi ptr [ %v4, %b2 ], [ %v53, %should_merge ]23 %v10 = phi i32 [ 0, %b2 ], [ %v30, %should_merge ]24 %v11 = phi ptr [ %a1, %b2 ], [ %v51, %should_merge ]25 %v12 = phi i32 [ 0, %b2 ], [ %v23, %should_merge ]26 %v13 = phi i32 [ 2, %b2 ], [ %v54, %should_merge ]27 %v14 = load i32, ptr %v11, align 4, !tbaa !028 %v15 = load i32, ptr %v9, align 4, !tbaa !029 %v16 = icmp ult i32 %v13, 3030 %v17 = zext i32 %v12 to i6431 %v18 = shl nuw i64 %v17, 3232 %v19 = zext i32 %v14 to i6433 %v20 = or i64 %v18, %v1934 %v21 = tail call i64 @llvm.hexagon.A2.addp(i64 %v20, i64 %v5)35 %v22 = lshr i64 %v21, 3236 %v23 = trunc i64 %v22 to i3237 %v24 = zext i32 %v10 to i6438 %v25 = shl nuw i64 %v24, 3239 %v26 = zext i32 %v15 to i6440 %v27 = or i64 %v25, %v2641 %v28 = tail call i64 @llvm.hexagon.A2.addp(i64 %v27, i64 %v5)42 %v29 = lshr i64 %v28, 3243 %v30 = trunc i64 %v29 to i3244 %v31 = getelementptr inbounds i32, ptr %a1, i32 %v1345 %v32 = load i32, ptr %v31, align 4, !tbaa !046 %v33 = or i32 %v13, 147 %v34 = getelementptr inbounds i32, ptr %a1, i32 %v3348 %v35 = load i32, ptr %v34, align 4, !tbaa !049 %v36 = zext i32 %v8 to i6450 %v37 = shl nuw i64 %v36, 3251 %v38 = zext i32 %v32 to i6452 %v39 = or i64 %v37, %v3853 %v40 = tail call i64 @llvm.hexagon.A2.subp(i64 %v39, i64 %v5)54 %v41 = lshr i64 %v40, 3255 %v42 = trunc i64 %v41 to i3256 %v43 = zext i32 %v7 to i6457 %v44 = shl nuw i64 %v43, 3258 %v45 = zext i32 %v35 to i6459 %v46 = or i64 %v44, %v4560 %v47 = tail call i64 @llvm.hexagon.A2.subp(i64 %v46, i64 %v5)61 %v48 = lshr i64 %v47, 3262 %v49 = trunc i64 %v48 to i3263 br i1 %v16, label %should_merge, label %exit64 65should_merge: ; preds = %loop66 %v50 = add nuw nsw i32 %v13, 267 %v51 = getelementptr inbounds i32, ptr %a1, i32 %v5068 %v52 = add nuw nsw i32 %v13, 369 %v53 = getelementptr inbounds i32, ptr %a1, i32 %v5270 %v54 = add nuw nsw i32 %v13, 471 br label %loop72 73exit: ; preds = %loop74 %v57 = tail call i64 @llvm.hexagon.A2.combinew(i32 %v42, i32 %v23)75 %v58 = tail call i64 @llvm.hexagon.A2.combinew(i32 %v49, i32 %v30)76 %v59 = tail call i64 @llvm.hexagon.A2.addp(i64 %v57, i64 %v58)77 %v60 = lshr i64 %v59, 3278 %v61 = trunc i64 %v60 to i3279 ret i32 %v6180}81 82declare i64 @llvm.hexagon.A2.addp(i64, i64) #183declare i64 @llvm.hexagon.A2.subp(i64, i64) #184declare i64 @llvm.hexagon.A2.combinew(i32, i32) #185 86attributes #0 = { nounwind readonly "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" }87attributes #1 = { nounwind readnone }88 89!0 = !{!1, !1, i64 0}90!1 = !{!"long", !2, i64 0}91!2 = !{!"omnipotent char", !3, i64 0}92!3 = !{!"Simple C/C++ TBAA"}93