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1; RUN: llc -mtriple=hexagon < %s | FileCheck %s2; REQUIRES: asserts3 4; Hexagon early if-conversion used to crash on this testcase due to not5; recognizing vector predicate registers.6 7target triple = "hexagon"8 9; Check that the early if-conversion has not happened.10 11; CHECK-LABEL: fred12; CHECK: q{{[0-3]}} = not13; CHECK: LBB14; CHECK: if (q{{[0-3]}}) vmem15define void @fred(i32 %a0) #0 {16b1:17 %v2 = tail call <128 x i1> @llvm.hexagon.V6.pred.scalar2.128B(i32 %a0) #218 br i1 undef, label %b3, label %b519 20b3: ; preds = %b121 %v4 = tail call <128 x i1> @llvm.hexagon.V6.pred.not.128B(<128 x i1> %v2) #222 br label %b523 24b5: ; preds = %b3, %b125 %v6 = phi <128 x i1> [ %v4, %b3 ], [ %v2, %b1 ]26 tail call void asm sideeffect "if ($0) vmem($1) = $2;", "q,r,v,~{memory}"(<128 x i1> %v6, ptr undef, <32 x i32> undef) #227 ret void28}29 30declare <128 x i1> @llvm.hexagon.V6.pred.scalar2.128B(i32) #131declare <128 x i1> @llvm.hexagon.V6.pred.not.128B(<128 x i1>) #132 33attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" }34attributes #1 = { nounwind readnone }35attributes #2 = { nounwind }36 37