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1; RUN: llc -O2 -mtriple=hexagon < %s | FileCheck %s2; Rely on the comments generated by llc. Check that "if.then" was predicated.3; CHECK: while.body134; CHECK: if{{.*}}memd5; CHECK: while.end6 7%struct.1 = type { i32, i32 }8%struct.2 = type { [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [3 x i32], [24 x i32], [8 x %struct.1], [5 x i32] }9 10@A1 = global i64 zeroinitializer11@A2 = global i64 zeroinitializer12@B1 = global i32 zeroinitializer13@B2 = global i32 zeroinitializer14@C1 = global i8 zeroinitializer15 16declare i32 @llvm.hexagon.S2.cl0(i32) nounwind readnone17declare i32 @llvm.hexagon.S2.setbit.r(i32, i32) nounwind readnone18declare i64 @llvm.hexagon.M2.vmpy2s.s0(i32, i32) nounwind readnone19declare i64 @llvm.hexagon.M2.vmac2s.s0(i64, i32, i32) nounwind readnone20declare i64 @llvm.hexagon.A2.vaddws(i64, i64) nounwind readnone21declare i64 @llvm.hexagon.A2.vsubws(i64, i64) nounwind readnone22declare i32 @llvm.hexagon.A4.modwrapu(i32, i32) nounwind readnone23 24define void @foo(i32 %n, ptr %ptr) #0 {25entry:26 br label %while.body27 28while.body:29 %count = phi i32 [ 0, %entry ], [ %next, %while.end ]30 %idx = phi i32 [ 0, %entry ], [ %15, %while.end ]31 %0 = load i32, ptr @B1, align 432 %1 = load i32, ptr @B2, align 833 %2 = and i32 %1, %034 br label %while.body1335 36while.body13: ; preds = %while.body, %if.end37 %3 = phi i64 [ %13, %if.end ], [ 0, %while.body ]38 %4 = phi i64 [ %14, %if.end ], [ 0, %while.body ]39 %m = phi i32 [ %6, %if.end ], [ %2, %while.body ]40 %5 = tail call i32 @llvm.hexagon.S2.cl0(i32 %m)41 %6 = tail call i32 @llvm.hexagon.S2.setbit.r(i32 %m, i32 %5)42 %cgep85 = getelementptr [10 x %struct.2], ptr inttoptr (i32 -121502345 to ptr), i32 0, i32 %idx43 %cgep90 = getelementptr %struct.2, ptr %cgep85, i32 0, i32 12, i32 %544 %7 = load i32, ptr %cgep90, align 445 %8 = tail call i64 @llvm.hexagon.M2.vmpy2s.s0(i32 %7, i32 %7)46 %cgep91 = getelementptr %struct.2, ptr %cgep85, i32 0, i32 13, i32 %547 %9 = load i32, ptr %cgep91, align 448 %10 = tail call i64 @llvm.hexagon.M2.vmac2s.s0(i64 %8, i32 %9, i32 %9)49 %11 = load i8, ptr @C1, align 150 %and24 = and i8 %11, 151 %cmp = icmp eq i8 %and24, 052 br i1 %cmp, label %if.then, label %if.end53 54if.then: ; preds = %while.body1355 %12 = tail call i64 @llvm.hexagon.A2.vaddws(i64 %3, i64 %10)56 store i64 %12, ptr %ptr, align 857 br label %if.end58 59if.end: ; preds = %if.then, %while.body1360 %13 = phi i64 [ %12, %if.then ], [ %3, %while.body13 ]61 %14 = tail call i64 @llvm.hexagon.A2.vsubws(i64 %4, i64 %10)62 %tobool12 = icmp eq i32 %6, 063 br i1 %tobool12, label %while.end, label %while.body1364 65while.end:66 %add40 = add i32 %idx, 167 %15 = tail call i32 @llvm.hexagon.A4.modwrapu(i32 %add40, i32 10) nounwind68 %next = add i32 %count, 169 %cc = icmp eq i32 %next, %n70 br i1 %cc, label %end, label %while.body71 72end:73 store i64 %10, ptr @A2, align 874 ret void75}76 77attributes #0 = { nounwind "target-cpu"="hexagonv5" }78