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1; RUN: llc -mtriple=hexagon -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s2 3; After register allocation it is possible to have a spill of a register4; that is only partially defined. That in itself it fine, but creates a5; problem for double vector registers. Stores of such registers are pseudo6; instructions that are expanded into pairs of individual vector stores,7; and in case of a partially defined source, one of the stores may use8; an entirely undefined register.9;10; This testcase used to crash. Make sure we can handle it, and that we11; do generate a store for the defined part of W0:12 13; CHECK-LABEL: fred:14; CHECK: v[[REG:[0-9]+]] = vsplat15; CHECK: vmem(r29+#{{[0-9]+}}) = v[[REG]]16 17 18target triple = "hexagon"19 20declare void @danny() local_unnamed_addr #021declare void @sammy() local_unnamed_addr #022declare <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32>) #123declare <32 x i32> @llvm.hexagon.V6.lvsplatw.128B(i32) #124declare <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32>, <32 x i32>) #125declare <32 x i32> @llvm.hexagon.V6.vshuffeb.128B(<32 x i32>, <32 x i32>) #126declare <32 x i32> @llvm.hexagon.V6.vlsrh.128B(<32 x i32>, i32) #127declare <64 x i32> @llvm.hexagon.V6.vaddh.dv.128B(<64 x i32>, <64 x i32>) #128 29define hidden void @fred() #2 {30b0:31 %v1 = load i32, ptr null, align 432 %v2 = icmp ult i64 0, 214748364833 br i1 %v2, label %b3, label %b534 35b3: ; preds = %b036 %v4 = icmp sgt i32 0, -137 br i1 %v4, label %b6, label %b538 39b5: ; preds = %b3, %b040 ret void41 42b6: ; preds = %b343 tail call void @danny()44 br label %b745 46b7: ; preds = %b21, %b647 %v8 = icmp sgt i32 %v1, 048 %v9 = select i1 %v8, i32 %v1, i32 049 %v10 = select i1 false, i32 0, i32 %v950 %v11 = icmp slt i32 %v10, 051 %v12 = select i1 %v11, i32 %v10, i32 052 %v13 = icmp slt i32 0, %v1253 br i1 %v13, label %b14, label %b1854 55b14: ; preds = %b16, %b756 br i1 false, label %b15, label %b1657 58b15: ; preds = %b1459 br label %b1660 61b16: ; preds = %b15, %b1462 %v17 = icmp eq i32 0, %v1263 br i1 %v17, label %b18, label %b1464 65b18: ; preds = %b16, %b766 tail call void @danny()67 %v19 = tail call <32 x i32> @llvm.hexagon.V6.lvsplatw.128B(i32 524296) #068 %v20 = tail call <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32> %v19, <32 x i32> %v19)69 br label %b2270 71b21: ; preds = %b2272 store volatile <64 x i32> %v20, ptr null73 tail call void @sammy() #374 br label %b775 76b22: ; preds = %b22, %b1877 %v23 = tail call <64 x i32> @llvm.hexagon.V6.vaddh.dv.128B(<64 x i32> zeroinitializer, <64 x i32> %v20) #078 %v24 = tail call <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32> %v23)79 %v25 = tail call <32 x i32> @llvm.hexagon.V6.vlsrh.128B(<32 x i32> %v24, i32 4) #080 %v26 = tail call <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32> zeroinitializer, <32 x i32> %v25)81 %v27 = tail call <32 x i32> @llvm.hexagon.V6.vshuffeb.128B(<32 x i32> zeroinitializer, <32 x i32> zeroinitializer) #082 %v28 = tail call <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32> %v26) #083 %v29 = tail call <32 x i32> @llvm.hexagon.V6.vshuffeb.128B(<32 x i32> zeroinitializer, <32 x i32> %v28) #084 store <32 x i32> %v27, ptr null, align 12885 %v30 = add nsw i32 0, 12886 %v31 = getelementptr inbounds i8, ptr null, i32 %v3087 store <32 x i32> %v29, ptr %v31, align 12888 %v33 = icmp eq i32 0, 089 br i1 %v33, label %b21, label %b2290}91 92attributes #0 = { nounwind }93attributes #1 = { nounwind readnone }94attributes #2 = { nounwind "reciprocal-estimates"="none" "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }95attributes #3 = { nobuiltin nounwind }96