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1; RUN: llc -mtriple=hexagon -hexagon-extract=0 -hexbit-extract=0 < %s | FileCheck %s2; Check that we generate fused logical and with shift instruction.3; Disable "extract" generation, since it may eliminate the and/lsr.4 5; CHECK: r{{[0-9]+}} = and(#15,lsr(r{{[0-9]+}},#{{[0-9]+}})6 7define i32 @main(ptr %a, ptr %b) nounwind {8 entry:9 %0 = load i16, ptr %a, align 210 %conv1 = sext i16 %0 to i3211 %shr1 = ashr i32 %conv1, 312 %and1 = and i32 %shr1, 1513 %conv2 = trunc i32 %and1 to i1614 store i16 %conv2, ptr %b, align 215 ret i32 016}17 18