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1; RUN: llc -mtriple=hexagon < %s | FileCheck %s2; Check that we generate load instructions with global + offset3 4 5%s.0 = type { i8, i8, i16, i32 }6 7@g0 = common global %s.0 zeroinitializer, align 48 9; CHECK-LABEL: f0:10; CHECK: r{{[0-9]+}} = memw(##g0+4)11define void @f0(i32 %a0, i32 %a1, ptr nocapture %a2) #0 {12b0:13 %v0 = icmp sgt i32 %a0, %a114 br i1 %v0, label %b1, label %b215 16b1: ; preds = %b017 %v1 = load i32, ptr getelementptr inbounds (%s.0, ptr @g0, i32 0, i32 3), align 418 store i32 %v1, ptr %a2, align 419 br label %b220 21b2: ; preds = %b1, %b022 ret void23}24 25; CHECK-LABEL: f1:26; CHECK: r{{[0-9]+}} = memub(##g0+1)27define void @f1(i32 %a0, i32 %a1, ptr nocapture %a2) #0 {28b0:29 %v0 = icmp sgt i32 %a0, %a130 br i1 %v0, label %b1, label %b231 32b1: ; preds = %b033 %v1 = load i8, ptr getelementptr inbounds (%s.0, ptr @g0, i32 0, i32 1), align 134 store i8 %v1, ptr %a2, align 135 br label %b236 37b2: ; preds = %b1, %b038 ret void39}40 41; CHECK-LABEL: f2:42; CHECK: r{{[0-9]+}} = memuh(##g0+2)43define void @f2(i32 %a0, i32 %a1, ptr %a2) #0 {44b0:45 %v0 = icmp sgt i32 %a0, %a146 br i1 %v0, label %b1, label %b247 48b1: ; preds = %b049 %v1 = load i16, ptr getelementptr inbounds (%s.0, ptr @g0, i32 0, i32 2), align 250 store i16 %v1, ptr %a2, align 251 br label %b252 53b2: ; preds = %b1, %b054 ret void55}56 57attributes #0 = { nounwind "target-cpu"="hexagonv5" }58