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1; RUN: llc -mtriple=hexagon < %s | FileCheck %s2; Check that we generate store instructions with global + offset3 4%s.0 = type { i8, i8, i16, i32 }5 6@g0 = common global %s.0 zeroinitializer, align 47 8; CHECK-LABEL: f0:9; CHECK: memb(##g0+1) = r{{[0-9]+}}10define void @f0(i32 %a0, i32 %a1, i8 zeroext %a2) #0 {11b0:12 %v0 = icmp sgt i32 %a0, %a113 br i1 %v0, label %b1, label %b214 15b1: ; preds = %b016 store i8 %a2, ptr getelementptr inbounds (%s.0, ptr @g0, i32 0, i32 1), align 117 br label %b218 19b2: ; preds = %b1, %b020 ret void21}22 23; CHECK-LABEL: f1:24; CHECK: memh(##g0+2) = r{{[0-9]+}}25define void @f1(i32 %a0, i32 %a1, i16 signext %a2) #0 {26b0:27 %v0 = icmp sgt i32 %a0, %a128 br i1 %v0, label %b1, label %b229 30b1: ; preds = %b031 store i16 %a2, ptr getelementptr inbounds (%s.0, ptr @g0, i32 0, i32 2), align 232 br label %b233 34b2: ; preds = %b1, %b035 ret void36}37 38attributes #0 = { nounwind "target-cpu"="hexagonv5" }39