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1; RUN: llc -mtriple=hexagon < %s | FileCheck %s2; Check that gp-relative instructions are being generated.3 4; CHECK: r{{[0-9]+}} = memw(gp+#g0)5; CHECK: r{{[0-9]+}} = memw(gp+#g1)6; CHECK: if (p{{[0-3]}}) memw(##g2) = r{{[0-9]+}}7 8@g0 = common global i32 0, align 49@g1 = common global i32 0, align 410@g2 = common global i32 0, align 411 12define i32 @f0(i32 %a0) #0 {13b0:14 %v0 = load i32, ptr @g0, align 415 %v1 = load i32, ptr @g1, align 416 %v2 = add nsw i32 %v1, %v017 %v3 = icmp eq i32 %v0, %v118 br i1 %v3, label %b2, label %b119 20b1: ; preds = %b021 %v4 = load i32, ptr @g2, align 422 br label %b323 24b2: ; preds = %b025 %v5 = add nsw i32 %v2, %v026 store i32 %v5, ptr @g2, align 427 br label %b328 29b3: ; preds = %b2, %b130 %v6 = phi i32 [ %v4, %b1 ], [ %v5, %b2 ]31 %v7 = icmp eq i32 %v2, %v632 %v8 = select i1 %v7, i32 %v6, i32 %v133 ret i32 %v834}35 36attributes #0 = { nounwind "target-cpu"="hexagonv5" }37