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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=hexagon < %s | FileCheck %s3 4; Test that we compile the HVX dual output intrinsics.5 6define inreg <16 x i32> @f0(<16 x i32> %a0, <16 x i32> %a1, ptr %a2) #0 {7; CHECK-LABEL: f0:8; CHECK: // %bb.0: // %b09; CHECK-NEXT: {10; CHECK-NEXT: r1 = #-111; CHECK-NEXT: v2 = vmem(r0+#0)12; CHECK-NEXT: }13; CHECK-NEXT: {14; CHECK-NEXT: q0 = vand(v2,r1)15; CHECK-NEXT: }16; CHECK-NEXT: {17; CHECK-NEXT: v0.w = vadd(v0.w,v1.w,q0):carry18; CHECK-NEXT: jumpr r3119; CHECK-NEXT: }20b0:21 %v0 = load <16 x i32>, ptr %a2, align 6422 %v1 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %v0, i32 -1)23 %v2 = tail call { <16 x i32>, <64 x i1> } @llvm.hexagon.V6.vaddcarry(<16 x i32> %a0, <16 x i32> %a1, <64 x i1> %v1)24 %v3 = extractvalue { <16 x i32>, <64 x i1> } %v2, 025 ret <16 x i32> %v326}27 28define inreg <16 x i32> @f1(<16 x i32> %a0, <16 x i32> %a1, ptr %a2) #0 {29; CHECK-LABEL: f1:30; CHECK: // %bb.0: // %b031; CHECK-NEXT: {32; CHECK-NEXT: r1 = #-133; CHECK-NEXT: v2 = vmem(r0+#0)34; CHECK-NEXT: }35; CHECK-NEXT: {36; CHECK-NEXT: q0 = vand(v2,r1)37; CHECK-NEXT: }38; CHECK-NEXT: {39; CHECK-NEXT: v0.w = vsub(v0.w,v1.w,q0):carry40; CHECK-NEXT: jumpr r3141; CHECK-NEXT: }42b0:43 %v0 = load <16 x i32>, ptr %a2, align 6444 %v1 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %v0, i32 -1)45 %v2 = tail call { <16 x i32>, <64 x i1> } @llvm.hexagon.V6.vsubcarry(<16 x i32> %a0, <16 x i32> %a1, <64 x i1> %v1)46 %v3 = extractvalue { <16 x i32>, <64 x i1> } %v2, 047 ret <16 x i32> %v348}49 50define inreg <16 x i32> @f2(<16 x i32> %a0, <16 x i32> %a1) #0 {51; CHECK-LABEL: f2:52; CHECK: // %bb.0: // %b053; CHECK-NEXT: {54; CHECK-NEXT: v0.w,q0 = vadd(v0.w,v1.w):carry55; CHECK-NEXT: jumpr r3156; CHECK-NEXT: }57b0:58 %v0 = tail call { <16 x i32>, <64 x i1> } @llvm.hexagon.V6.vaddcarryo(<16 x i32> %a0, <16 x i32> %a1)59 %v1 = extractvalue { <16 x i32>, <64 x i1> } %v0, 060 ret <16 x i32> %v161}62 63define inreg <16 x i32> @f3(<16 x i32> %a0, <16 x i32> %a1) #0 {64; CHECK-LABEL: f3:65; CHECK: // %bb.0: // %b066; CHECK-NEXT: {67; CHECK-NEXT: v0.w,q0 = vsub(v0.w,v1.w):carry68; CHECK-NEXT: jumpr r3169; CHECK-NEXT: }70b0:71 %v0 = tail call { <16 x i32>, <64 x i1> } @llvm.hexagon.V6.vsubcarryo(<16 x i32> %a0, <16 x i32> %a1)72 %v1 = extractvalue { <16 x i32>, <64 x i1> } %v0, 073 ret <16 x i32> %v174}75 76declare { <16 x i32>, <64 x i1> } @llvm.hexagon.V6.vaddcarry(<16 x i32>, <16 x i32>, <64 x i1>) #177declare { <16 x i32>, <64 x i1> } @llvm.hexagon.V6.vsubcarry(<16 x i32>, <16 x i32>, <64 x i1>) #178declare { <16 x i32>, <64 x i1> } @llvm.hexagon.V6.vaddcarryo(<16 x i32>, <16 x i32>) #179declare { <16 x i32>, <64 x i1> } @llvm.hexagon.V6.vsubcarryo(<16 x i32>, <16 x i32>) #180 81declare <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32>, i32) #182 83attributes #0 = { nounwind "target-cpu"="hexagonv66" "target-features"="+hvxv66,+hvx-length64b" }84attributes #1 = { nounwind readnone }85