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1;; RUN: llc --mtriple=hexagon --mcpu=hexagonv81 --mattr=+hvxv81,+hvx-length128b %s -o - | FileCheck %s2 3define void @mul_and_sub_1(ptr readonly %A, ptr readonly %B, ptr readonly %C, ptr writeonly %D) {4entry:5 %AVec = load <32 x float>, ptr %A, align 46 %BVec = load <32 x float>, ptr %B, align 47 %CVec = load <32 x float>, ptr %C, align 48 %AtBVec = fmul <32 x float> %AVec, %BVec9 10 %DVec = fsub <32 x float> %CVec, %AtBVec11 store <32 x float> %DVec, ptr %D, align 412 ret void13}14;; CHECK: mul_and_sub_115;; CHECK: vsub(v{{[0-9]+}}.sf,v{{[0-9]+}}.qf32)16 17 18define void @mul_and_sub_2(ptr readonly %A, ptr readonly %B, ptr readonly %C, ptr writeonly %D) {19entry:20 %AVec = load <32 x float>, ptr %A, align 421 %BVec = load <32 x float>, ptr %B, align 422 %CVec = load <32 x float>, ptr %C, align 423 %AtBVec = fmul <32 x float> %AVec, %BVec24 25 %DVec = fsub <32 x float> %AtBVec, %CVec26 store <32 x float> %DVec, ptr %D, align 427 ret void28}29;; CHECK: mul_and_sub_230;; CHECK: vsub(v{{[0-9]+}}.qf32,v{{[0-9]+}}.sf)31 32 33define void @mul_and_sub_3(ptr readonly %A, ptr readonly %B, ptr readonly %C, ptr writeonly %D) {34entry:35 %AVec = load <64 x half>, ptr %A, align 436 %BVec = load <64 x half>, ptr %B, align 437 %CVec = load <64 x half>, ptr %C, align 438 %AtBVec = fmul <64 x half> %AVec, %BVec39 40 %DVec = fsub <64 x half> %CVec, %AtBVec41 store <64 x half> %DVec, ptr %D, align 442 ret void43}44;; CHECK: mul_and_sub_345;; CHECK: vsub(v{{[0-9]+}}.hf,v{{[0-9]+}}.qf16)46 47 48define void @mul_and_sub_4(ptr readonly %A, ptr readonly %B, ptr readonly %C, ptr writeonly %D) {49entry:50 %AVec = load <64 x half>, ptr %A, align 451 %BVec = load <64 x half>, ptr %B, align 452 %CVec = load <64 x half>, ptr %C, align 453 %AtBVec = fmul <64 x half> %AVec, %BVec54 55 %DVec = fsub <64 x half> %AtBVec, %CVec56 store <64 x half> %DVec, ptr %D, align 457 ret void58}59;; CHECK: mul_and_sub_460;; CHECK: vsub(v{{[0-9]+}}.qf16,v{{[0-9]+}}.hf)61