33 lines · plain
1; RUN: llc -mtriple=hexagon < %s | FileCheck %s2 3; Test that V_vzero and W_vzero intrinsics work. The W_vzero intrinsic was added4; for v65/hvx.5 6 7; CHECK-LABEL: f0:8; CHECK: [[VREG1:v([0-9]+)]] = vxor([[VREG1]],[[VREG1]])9define void @f0(ptr nocapture %a0) #0 {10b0:11 %v1 = tail call <16 x i32> @llvm.hexagon.V6.vd0()12 store <16 x i32> %v1, ptr %a0, align 6413 ret void14}15 16; Function Attrs: nounwind readnone17declare <16 x i32> @llvm.hexagon.V6.vd0() #118 19; CHECK-LABEL: f1:20; CHECK: [[VREG2:v([0-9]+):([0-9]+).w]] = vsub([[VREG2]],[[VREG2]])21define void @f1(ptr nocapture %a0) #0 {22b0:23 %v1 = tail call <32 x i32> @llvm.hexagon.V6.vdd0()24 store <32 x i32> %v1, ptr %a0, align 12825 ret void26}27 28; Function Attrs: nounwind readnone29declare <32 x i32> @llvm.hexagon.V6.vdd0() #130 31attributes #0 = { nounwind "target-cpu"="hexagonv65" "target-features"="+hvxv65,+hvx-length64b" }32attributes #1 = { nounwind readnone }33