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1; RUN: llc -mtriple=hexagon < %s | FileCheck %s2;3; Check that we do not generate v0 = vand(v1,v1)4 5; CHECK-NOT: v{{[0-9]+}} = vand(v{{[0-9]+}},v{{[0-9]+}})6 7; Function Attrs: nounwind8define void @f0(ptr nocapture readonly %a0, ptr nocapture readonly %a1, i32 %a2, ptr nocapture %a3, i32 %a4, i32 %a5) #0 {9b0:10 %v1 = load i64, ptr %a1, align 8, !tbaa !011 %v2 = shl i64 %v1, 812 %v3 = trunc i64 %v2 to i3213 %v4 = trunc i64 %v1 to i3214 %v5 = and i32 %v4, 1677721515 %v7 = load <16 x i32>, ptr %a0, align 64, !tbaa !416 %v8 = getelementptr inbounds i8, ptr %a0, i32 3217 %v10 = load <16 x i32>, ptr %v8, align 64, !tbaa !418 %v11 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v10, <16 x i32> %v7)19 %v12 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi(<32 x i32> %v11, i32 %v5, i32 0)20 %v13 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi(<32 x i32> %v11, i32 %v3, i32 0)21 %v14 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v12)22 %v15 = tail call <16 x i32> @llvm.hexagon.V6.vasrwuhsat(<16 x i32> %v14, <16 x i32> %v14, i32 %a2)23 %v16 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v13)24 %v17 = tail call <16 x i32> @llvm.hexagon.V6.vasrwuhsat(<16 x i32> %v16, <16 x i32> %v16, i32 %a2)25 %v18 = getelementptr inbounds i8, ptr %a3, i32 3226 store <16 x i32> %v15, ptr %v18, align 64, !tbaa !427 store <16 x i32> %v17, ptr %a3, align 64, !tbaa !428 ret void29}30 31; Function Attrs: nounwind readnone32declare <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32>, <16 x i32>) #133 34; Function Attrs: nounwind readnone35declare <32 x i32> @llvm.hexagon.V6.vrmpybusi(<32 x i32>, i32, i32) #136 37; Function Attrs: nounwind readnone38declare <16 x i32> @llvm.hexagon.V6.vasrwuhsat(<16 x i32>, <16 x i32>, i32) #139 40; Function Attrs: nounwind readnone41declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #142 43; Function Attrs: nounwind readnone44declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #145 46; Function Attrs: nounwind readnone47define i32 @f1() #2 {48b0:49 ret i32 050}51 52attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }53attributes #1 = { nounwind readnone }54attributes #2 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }55 56!0 = !{!1, !1, i64 0}57!1 = !{!"long long", !2, i64 0}58!2 = !{!"omnipotent char", !3, i64 0}59!3 = !{!"Simple C/C++ TBAA"}60!4 = !{!2, !2, i64 0}61