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1;; RUN: llc --mtriple=hexagon -mattr=+hvxv79,+hvx-length128b %s -o - | FileCheck %s2 3define dso_local void @store_isnan_f32(ptr %a, ptr %b, ptr %isnan_cmp) local_unnamed_addr {4entry:5 %arrayidx_a = getelementptr inbounds nuw float, ptr %a, i32 06 %arrayidx_b = getelementptr inbounds nuw float, ptr %b, i32 07 %0 = load <32 x float>, ptr %arrayidx_a, align 48 %1 = load <32 x float>, ptr %arrayidx_b, align 49 %.vectorized = fcmp uno <32 x float> %0, %110 %.LS.instance = zext <32 x i1> %.vectorized to <32 x i32>11 %arrayidx1 = getelementptr inbounds nuw i32, ptr %isnan_cmp, i32 012 store <32 x i32> %.LS.instance, ptr %arrayidx1, align 413 ret void14}15 16; CHECK: store_isnan_f3217; CHECK: [[RONE32:r[0-9]+]] = #118; CHECK: [[VOP2_F32:v[0-9]+]] = vxor([[VOP2_F32]],[[VOP2_F32]])19; CHECK: [[VOP1_F32:v[0-9]+]] = vmemu(r0+#0)20; CHECK: [[VONES32:v[0-9]+]] = vsplat([[RONE32]])21; CHECK: [[Q1_F32:q[0-9]+]] = vcmp.eq([[VOP1_F32]].w,[[VOP1_F32]].w)22; CHECK: [[VOP3_F32:v[0-9]+]] = vmemu(r1+#0)23; CHECK: [[Q1_F32]] &= vcmp.eq([[VOP3_F32]].w,[[VOP3_F32]].w)24; CHECK: [[VOUT_F32:v[0-9]+]] = vmux([[Q1_F32]],[[VOP2_F32]],[[VONES32]])25; CHECK: vmemu(r2+#0) = [[VOUT_F32]]26 27define dso_local void @store_isnan_f16(ptr %a, ptr %b, ptr %isnan_cmp) local_unnamed_addr {28entry:29 %arrayidx_a = getelementptr inbounds nuw half, ptr %a, i32 030 %arrayidx_b = getelementptr inbounds nuw half, ptr %b, i32 031 %0 = load <64 x half>, ptr %arrayidx_a, align 232 %1 = load <64 x half>, ptr %arrayidx_b, align 233 %.vectorized = fcmp uno <64 x half> %0, %134 %conv.LS.instance = zext <64 x i1> %.vectorized to <64 x i16>35 %arrayidx1 = getelementptr inbounds nuw i16, ptr %isnan_cmp, i32 036 store <64 x i16> %conv.LS.instance, ptr %arrayidx1, align 237 ret void38}39; CHECK-LABEL: store_isnan_f1640; CHECK: [[RONE16:r[0-9]+]] = #141; CHECK: [[VOP2_F16:v[0-9]+]] = vxor([[VOP2_F16]],[[VOP2_F16]])42; CHECK: [[VOP1_F16:v[0-9]+]] = vmemu(r0+#0)43; CHECK: [[VONES16:v[0-9]+]].h = vsplat([[RONE16]])44; CHECK: [[Q1_F16:q[0-9]+]] = vcmp.eq([[VOP1_F16]].h,[[VOP1_F16]].h)45; CHECK: [[VOP3_F16:v[0-9]+]] = vmemu(r1+#0)46; CHECK: [[Q1_F16]] &= vcmp.eq([[VOP3_F16]].h,[[VOP3_F16]].h)47; CHECK: [[VOUT_F16:v[0-9]+]] = vmux([[Q1_F16]],[[VOP2_F16]],[[VONES16]])48; CHECK: vmemu(r2+#0) = [[VOUT_F32]]49 50define dso_local void @store_isordered_f32(ptr %a, ptr %b, ptr %isordered_cmp) local_unnamed_addr {51entry:52 %arrayidx_a = getelementptr inbounds nuw float, ptr %a, i32 053 %arrayidx_b = getelementptr inbounds nuw float, ptr %b, i32 054 %0 = load <32 x float>, ptr %arrayidx_a, align 455 %1 = load <32 x float>, ptr %arrayidx_b, align 456 %.vectorized = fcmp ord <32 x float> %0, %157 %.LS.instance = zext <32 x i1> %.vectorized to <32 x i32>58 %arrayidx1 = getelementptr inbounds nuw i32, ptr %isordered_cmp, i32 059 store <32 x i32> %.LS.instance, ptr %arrayidx1, align 460 ret void61}62; CHECK-LABEL: store_isordered_f3263; CHECK: [[VOP2_ORD_F32:v[0-9]+]] = vxor([[VOP2_ORD_F32]],[[VOP2_ORD_F32]])64; CHECK: [[VOP1_ORD_F32:v[0-9]+]] = vmemu(r0+#0)65; CHECK: [[VONES_ORD_F32:v[0-9]+]] = vsplat([[RONE32]])66; CHECK: [[Q1_ORD_F32:q[0-9]+]] = vcmp.eq([[VOP1_ORD_F32]].w,[[VOP1_ORD_F32]].w)67; CHECK: [[VOP3_ORD_F32:v[0-9]+]] = vmemu(r1+#0)68; CHECK: [[Q1_ORD_F32]] &= vcmp.eq([[VOP3_ORD_F32]].w,[[VOP3_ORD_F32]].w)69; CHECK: [[VOUT_ORD_F32:v[0-9]+]] = vmux([[Q1_ORD_F32]],[[VONES_ORD_F32]],[[VOP2_ORD_F32]])70; CHECK: vmemu(r2+#0) = [[VOUT_ORD_F32]]71 72 73define dso_local void @store_isordered_f16(ptr %a, ptr %b, ptr %isordered_cmp) local_unnamed_addr {74entry:75 %arrayidx_a = getelementptr inbounds nuw half, ptr %a, i32 076 %arrayidx_b = getelementptr inbounds nuw half, ptr %b, i32 077 %0 = load <64 x half>, ptr %arrayidx_a, align 278 %1 = load <64 x half>, ptr %arrayidx_b, align 279 %.vectorized = fcmp ord <64 x half> %0, %180 %conv.LS.instance = zext <64 x i1> %.vectorized to <64 x i16>81 %arrayidx1 = getelementptr inbounds nuw i16, ptr %isordered_cmp, i32 082 store <64 x i16> %conv.LS.instance, ptr %arrayidx1, align 283 ret void84}85; CHECK-LABEL: store_isordered_f1686; CHECK: [[VOP2_ORD_F16:v[0-9]+]] = vxor([[VOP2_ORD_F16]],[[VOP2_ORD_F16]])87; CHECK: [[VOP1_ORD_F16:v[0-9]+]] = vmemu(r0+#0)88; CHECK: [[VONES_ORD_F16:v[0-9]+]].h = vsplat([[RONE16]])89; CHECK: [[Q1_ORD_F16:q[0-9]+]] = vcmp.eq([[VOP1_ORD_F16]].h,[[VOP1_ORD_F16]].h)90; CHECK: [[VOP3_ORD_F16:v[0-9]+]] = vmemu(r1+#0)91; CHECK: [[Q1_ORD_F16]] &= vcmp.eq([[VOP3_ORD_F16]].h,[[VOP3_ORD_F16]].h)92; CHECK: [[VOUT_ORD_F16:v[0-9]+]] = vmux([[Q1_ORD_F16]],[[VONES_ORD_F16]],[[VOP2_ORD_F16]])93; CHECK: vmemu(r2+#0) = [[VOUT_ORD_F16]]94