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1; RUN: llc -mtriple=hexagon < %s | FileCheck %s2 3; CHECK-LABEL: test1:4; CHECK: v{{[0-9]+}} = vand(v{{[0-9]+}},v{{[0-9]+}})5define <16 x i32> @test1(<16 x i32> %a, <16 x i32> %b) #0 {6entry:7 %0 = tail call <16 x i32> @llvm.hexagon.V6.vand(<16 x i32> %a, <16 x i32> %b)8 ret <16 x i32> %09}10 11; CHECK-LABEL: test2:12; CHECK: v{{[0-9]+}} = vor(v{{[0-9]+}},v{{[0-9]+}})13define <16 x i32> @test2(<16 x i32> %a, <16 x i32> %b) #0 {14entry:15 %0 = tail call <16 x i32> @llvm.hexagon.V6.vor(<16 x i32> %a, <16 x i32> %b)16 ret <16 x i32> %017}18 19; CHECK-LABEL: test3:20; CHECK: v{{[0-9]+}} = vxor(v{{[0-9]+}},v{{[0-9]+}})21define <16 x i32> @test3(<16 x i32> %a, <16 x i32> %b) #0 {22entry:23 %0 = tail call <16 x i32> @llvm.hexagon.V6.vxor(<16 x i32> %a, <16 x i32> %b)24 ret <16 x i32> %025}26 27; CHECK-LABEL: test4:28; CHECK: v{{[0-9]+}}.w = vadd(v{{[0-9]+}}.w,v{{[0-9]+}}.w)29define <16 x i32> @test4(<16 x i32> %a, <16 x i32> %b) #0 {30entry:31 %0 = tail call <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32> %a, <16 x i32> %b)32 ret <16 x i32> %033}34 35; CHECK-LABEL: test5:36; CHECK: v{{[0-9]+}}.ub = vadd(v{{[0-9]+}}.ub,v{{[0-9]+}}.ub):sat37define <16 x i32> @test5(<16 x i32> %a, <16 x i32> %b) #0 {38entry:39 %0 = tail call <16 x i32> @llvm.hexagon.V6.vaddubsat(<16 x i32> %a, <16 x i32> %b)40 ret <16 x i32> %041}42 43; CHECK-LABEL: test6:44; CHECK: v{{[0-9]+}}.uh = vadd(v{{[0-9]+}}.uh,v{{[0-9]+}}.uh):sat45define <16 x i32> @test6(<16 x i32> %a, <16 x i32> %b) #0 {46entry:47 %0 = tail call <16 x i32> @llvm.hexagon.V6.vadduhsat(<16 x i32> %a, <16 x i32> %b)48 ret <16 x i32> %049}50 51; CHECK-LABEL: test7:52; CHECK: v{{[0-9]+}}.h = vadd(v{{[0-9]+}}.h,v{{[0-9]+}}.h):sat53define <16 x i32> @test7(<16 x i32> %a, <16 x i32> %b) #0 {54entry:55 %0 = tail call <16 x i32> @llvm.hexagon.V6.vaddhsat(<16 x i32> %a, <16 x i32> %b)56 ret <16 x i32> %057}58 59; CHECK-LABEL: test8:60; CHECK: v{{[0-9]+}}.w = vadd(v{{[0-9]+}}.w,v{{[0-9]+}}.w):sat61define <16 x i32> @test8(<16 x i32> %a, <16 x i32> %b) #0 {62entry:63 %0 = tail call <16 x i32> @llvm.hexagon.V6.vaddwsat(<16 x i32> %a, <16 x i32> %b)64 ret <16 x i32> %065}66 67; CHECK-LABEL: test9:68; CHECK: v{{[0-9]+}}.b = vsub(v{{[0-9]+}}.b,v{{[0-9]+}}.b)69define <16 x i32> @test9(<16 x i32> %a, <16 x i32> %b) #0 {70entry:71 %0 = tail call <16 x i32> @llvm.hexagon.V6.vsubb(<16 x i32> %a, <16 x i32> %b)72 ret <16 x i32> %073}74 75; CHECK-LABEL: test10:76; CHECK: v{{[0-9]+}}.h = vsub(v{{[0-9]+}}.h,v{{[0-9]+}}.h)77define <16 x i32> @test10(<16 x i32> %a, <16 x i32> %b) #0 {78entry:79 %0 = tail call <16 x i32> @llvm.hexagon.V6.vsubh(<16 x i32> %a, <16 x i32> %b)80 ret <16 x i32> %081}82 83; CHECK-LABEL: test11:84; CHECK: v{{[0-9]+}}.w = vsub(v{{[0-9]+}}.w,v{{[0-9]+}}.w)85define <16 x i32> @test11(<16 x i32> %a, <16 x i32> %b) #0 {86entry:87 %0 = tail call <16 x i32> @llvm.hexagon.V6.vsubw(<16 x i32> %a, <16 x i32> %b)88 ret <16 x i32> %089}90 91; CHECK-LABEL: test12:92; CHECK: v{{[0-9]+}}.ub = vsub(v{{[0-9]+}}.ub,v{{[0-9]+}}.ub):sat93define <16 x i32> @test12(<16 x i32> %a, <16 x i32> %b) #0 {94entry:95 %0 = tail call <16 x i32> @llvm.hexagon.V6.vsububsat(<16 x i32> %a, <16 x i32> %b)96 ret <16 x i32> %097}98 99; CHECK-LABEL: test13:100; CHECK: v{{[0-9]+}}.uh = vsub(v{{[0-9]+}}.uh,v{{[0-9]+}}.uh):sat101define <16 x i32> @test13(<16 x i32> %a, <16 x i32> %b) #0 {102entry:103 %0 = tail call <16 x i32> @llvm.hexagon.V6.vsubuhsat(<16 x i32> %a, <16 x i32> %b)104 ret <16 x i32> %0105}106 107; CHECK-LABEL: test14:108; CHECK: v{{[0-9]+}}.h = vsub(v{{[0-9]+}}.h,v{{[0-9]+}}.h):sat109define <16 x i32> @test14(<16 x i32> %a, <16 x i32> %b) #0 {110entry:111 %0 = tail call <16 x i32> @llvm.hexagon.V6.vsubhsat(<16 x i32> %a, <16 x i32> %b)112 ret <16 x i32> %0113}114 115; CHECK-LABEL: test15:116; CHECK: v{{[0-9]+}}.w = vsub(v{{[0-9]+}}.w,v{{[0-9]+}}.w):sat117define <16 x i32> @test15(<16 x i32> %a, <16 x i32> %b) #0 {118entry:119 %0 = tail call <16 x i32> @llvm.hexagon.V6.vsubwsat(<16 x i32> %a, <16 x i32> %b)120 ret <16 x i32> %0121}122 123; CHECK-LABEL: test16:124; CHECK: v{{[0-9]+}}:{{[0-9]+}}.b = vadd(v{{[0-9]+}}:{{[0-9]+}}.b,v{{[0-9]+}}:{{[0-9]+}}.b)125define <32 x i32> @test16(<32 x i32> %a, <32 x i32> %b) #0 {126entry:127 %0 = tail call <32 x i32> @llvm.hexagon.V6.vaddb.dv(<32 x i32> %a, <32 x i32> %b)128 ret <32 x i32> %0129}130 131; CHECK-LABEL: test17:132; CHECK: v{{[0-9]+}}:{{[0-9]+}}.h = vadd(v{{[0-9]+}}:{{[0-9]+}}.h,v{{[0-9]+}}:{{[0-9]+}}.h)133define <32 x i32> @test17(<32 x i32> %a, <32 x i32> %b) #0 {134entry:135 %0 = tail call <32 x i32> @llvm.hexagon.V6.vaddh.dv(<32 x i32> %a, <32 x i32> %b)136 ret <32 x i32> %0137}138 139; CHECK-LABEL: test18:140; CHECK: v{{[0-9]+}}:{{[0-9]+}}.w = vadd(v{{[0-9]+}}:{{[0-9]+}}.w,v{{[0-9]+}}:{{[0-9]+}}.w)141define <32 x i32> @test18(<32 x i32> %a, <32 x i32> %b) #0 {142entry:143 %0 = tail call <32 x i32> @llvm.hexagon.V6.vaddw.dv(<32 x i32> %a, <32 x i32> %b)144 ret <32 x i32> %0145}146 147; CHECK-LABEL: test19:148; CHECK: v{{[0-9]+}}:{{[0-9]+}}.ub = vadd(v{{[0-9]+}}:{{[0-9]+}}.ub,v{{[0-9]+}}:{{[0-9]+}}.ub):sat149define <32 x i32> @test19(<32 x i32> %a, <32 x i32> %b) #0 {150entry:151 %0 = tail call <32 x i32> @llvm.hexagon.V6.vaddubsat.dv(<32 x i32> %a, <32 x i32> %b)152 ret <32 x i32> %0153}154 155; CHECK-LABEL: test20:156; CHECK: v{{[0-9]+}}:{{[0-9]+}}.uh = vadd(v{{[0-9]+}}:{{[0-9]+}}.uh,v{{[0-9]+}}:{{[0-9]+}}.uh):sat157define <32 x i32> @test20(<32 x i32> %a, <32 x i32> %b) #0 {158entry:159 %0 = tail call <32 x i32> @llvm.hexagon.V6.vadduhsat.dv(<32 x i32> %a, <32 x i32> %b)160 ret <32 x i32> %0161}162 163; CHECK-LABEL: test21:164; CHECK: v{{[0-9]+}}:{{[0-9]+}}.h = vadd(v{{[0-9]+}}:{{[0-9]+}}.h,v{{[0-9]+}}:{{[0-9]+}}.h):sat165define <32 x i32> @test21(<32 x i32> %a, <32 x i32> %b) #0 {166entry:167 %0 = tail call <32 x i32> @llvm.hexagon.V6.vaddhsat.dv(<32 x i32> %a, <32 x i32> %b)168 ret <32 x i32> %0169}170 171; CHECK-LABEL: test22:172; CHECK: v{{[0-9]+}}:{{[0-9]+}}.w = vadd(v{{[0-9]+}}:{{[0-9]+}}.w,v{{[0-9]+}}:{{[0-9]+}}.w):sat173define <32 x i32> @test22(<32 x i32> %a, <32 x i32> %b) #0 {174entry:175 %0 = tail call <32 x i32> @llvm.hexagon.V6.vaddwsat.dv(<32 x i32> %a, <32 x i32> %b)176 ret <32 x i32> %0177}178 179; CHECK-LABEL: test23:180; CHECK: v{{[0-9]+}}:{{[0-9]+}}.b = vsub(v{{[0-9]+}}:{{[0-9]+}}.b,v{{[0-9]+}}:{{[0-9]+}}.b)181define <32 x i32> @test23(<32 x i32> %a, <32 x i32> %b) #0 {182entry:183 %0 = tail call <32 x i32> @llvm.hexagon.V6.vsubb.dv(<32 x i32> %a, <32 x i32> %b)184 ret <32 x i32> %0185}186 187; CHECK-LABEL: test24:188; CHECK: v{{[0-9]+}}:{{[0-9]+}}.h = vsub(v{{[0-9]+}}:{{[0-9]+}}.h,v{{[0-9]+}}:{{[0-9]+}}.h)189define <32 x i32> @test24(<32 x i32> %a, <32 x i32> %b) #0 {190entry:191 %0 = tail call <32 x i32> @llvm.hexagon.V6.vsubh.dv(<32 x i32> %a, <32 x i32> %b)192 ret <32 x i32> %0193}194 195; CHECK-LABEL: test25:196; CHECK: v{{[0-9]+}}:{{[0-9]+}}.w = vsub(v{{[0-9]+}}:{{[0-9]+}}.w,v{{[0-9]+}}:{{[0-9]+}}.w)197define <32 x i32> @test25(<32 x i32> %a, <32 x i32> %b) #0 {198entry:199 %0 = tail call <32 x i32> @llvm.hexagon.V6.vsubw.dv(<32 x i32> %a, <32 x i32> %b)200 ret <32 x i32> %0201}202 203; CHECK-LABEL: test26:204; CHECK: v{{[0-9]+}}:{{[0-9]+}}.ub = vsub(v{{[0-9]+}}:{{[0-9]+}}.ub,v{{[0-9]+}}:{{[0-9]+}}.ub):sat205define <32 x i32> @test26(<32 x i32> %a, <32 x i32> %b) #0 {206entry:207 %0 = tail call <32 x i32> @llvm.hexagon.V6.vsububsat.dv(<32 x i32> %a, <32 x i32> %b)208 ret <32 x i32> %0209}210 211; CHECK-LABEL: test27:212; CHECK: v{{[0-9]+}}:{{[0-9]+}}.uh = vsub(v{{[0-9]+}}:{{[0-9]+}}.uh,v{{[0-9]+}}:{{[0-9]+}}.uh):sat213define <32 x i32> @test27(<32 x i32> %a, <32 x i32> %b) #0 {214entry:215 %0 = tail call <32 x i32> @llvm.hexagon.V6.vsubuhsat.dv(<32 x i32> %a, <32 x i32> %b)216 ret <32 x i32> %0217}218 219; CHECK-LABEL: test28:220; CHECK: v{{[0-9]+}}:{{[0-9]+}}.h = vsub(v{{[0-9]+}}:{{[0-9]+}}.h,v{{[0-9]+}}:{{[0-9]+}}.h):sat221define <32 x i32> @test28(<32 x i32> %a, <32 x i32> %b) #0 {222entry:223 %0 = tail call <32 x i32> @llvm.hexagon.V6.vsubhsat.dv(<32 x i32> %a, <32 x i32> %b)224 ret <32 x i32> %0225}226 227; CHECK-LABEL: test29:228; CHECK: v{{[0-9]+}}:{{[0-9]+}}.w = vsub(v{{[0-9]+}}:{{[0-9]+}}.w,v{{[0-9]+}}:{{[0-9]+}}.w):sat229define <32 x i32> @test29(<32 x i32> %a, <32 x i32> %b) #0 {230entry:231 %0 = tail call <32 x i32> @llvm.hexagon.V6.vsubwsat.dv(<32 x i32> %a, <32 x i32> %b)232 ret <32 x i32> %0233}234 235; CHECK-LABEL: test30:236; CHECK: v{{[0-9]+}}:{{[0-9]+}}.h = vadd(v{{[0-9]+}}.ub,v{{[0-9]+}}.ub)237define <32 x i32> @test30(<16 x i32> %a, <16 x i32> %b) #0 {238entry:239 %0 = tail call <32 x i32> @llvm.hexagon.V6.vaddubh(<16 x i32> %a, <16 x i32> %b)240 ret <32 x i32> %0241}242 243; CHECK-LABEL: test31:244; CHECK: v{{[0-9]+}}:{{[0-9]+}}.w = vadd(v{{[0-9]+}}.uh,v{{[0-9]+}}.uh)245define <32 x i32> @test31(<16 x i32> %a, <16 x i32> %b) #0 {246entry:247 %0 = tail call <32 x i32> @llvm.hexagon.V6.vadduhw(<16 x i32> %a, <16 x i32> %b)248 ret <32 x i32> %0249}250 251; CHECK-LABEL: test32:252; CHECK: v{{[0-9]+}}:{{[0-9]+}}.w = vadd(v{{[0-9]+}}.h,v{{[0-9]+}}.h)253define <32 x i32> @test32(<16 x i32> %a, <16 x i32> %b) #0 {254entry:255 %0 = tail call <32 x i32> @llvm.hexagon.V6.vaddhw(<16 x i32> %a, <16 x i32> %b)256 ret <32 x i32> %0257}258 259; CHECK-LABEL: test33:260; CHECK: v{{[0-9]+}}:{{[0-9]+}}.h = vsub(v{{[0-9]+}}.ub,v{{[0-9]+}}.ub)261define <32 x i32> @test33(<16 x i32> %a, <16 x i32> %b) #0 {262entry:263 %0 = tail call <32 x i32> @llvm.hexagon.V6.vsububh(<16 x i32> %a, <16 x i32> %b)264 ret <32 x i32> %0265}266 267; CHECK-LABEL: test34:268; CHECK: v{{[0-9]+}}:{{[0-9]+}}.w = vsub(v{{[0-9]+}}.uh,v{{[0-9]+}}.uh)269define <32 x i32> @test34(<16 x i32> %a, <16 x i32> %b) #0 {270entry:271 %0 = tail call <32 x i32> @llvm.hexagon.V6.vsubuhw(<16 x i32> %a, <16 x i32> %b)272 ret <32 x i32> %0273}274 275; CHECK-LABEL: test35:276; CHECK: v{{[0-9]+}}:{{[0-9]+}}.w = vsub(v{{[0-9]+}}.h,v{{[0-9]+}}.h)277define <32 x i32> @test35(<16 x i32> %a, <16 x i32> %b) #0 {278entry:279 %0 = tail call <32 x i32> @llvm.hexagon.V6.vsubhw(<16 x i32> %a, <16 x i32> %b)280 ret <32 x i32> %0281}282 283; CHECK-LABEL: test36:284; CHECK: v{{[0-9]+}}.ub = vabsdiff(v{{[0-9]+}}.ub,v{{[0-9]+}}.ub)285define <16 x i32> @test36(<16 x i32> %a, <16 x i32> %b) #0 {286entry:287 %0 = tail call <16 x i32> @llvm.hexagon.V6.vabsdiffub(<16 x i32> %a, <16 x i32> %b)288 ret <16 x i32> %0289}290 291; CHECK-LABEL: test37:292; CHECK: v{{[0-9]+}}.uh = vabsdiff(v{{[0-9]+}}.h,v{{[0-9]+}}.h)293define <16 x i32> @test37(<16 x i32> %a, <16 x i32> %b) #0 {294entry:295 %0 = tail call <16 x i32> @llvm.hexagon.V6.vabsdiffh(<16 x i32> %a, <16 x i32> %b)296 ret <16 x i32> %0297}298 299; CHECK-LABEL: test38:300; CHECK: v{{[0-9]+}}.uh = vabsdiff(v{{[0-9]+}}.uh,v{{[0-9]+}}.uh)301define <16 x i32> @test38(<16 x i32> %a, <16 x i32> %b) #0 {302entry:303 %0 = tail call <16 x i32> @llvm.hexagon.V6.vabsdiffuh(<16 x i32> %a, <16 x i32> %b)304 ret <16 x i32> %0305}306 307; CHECK-LABEL: test39:308; CHECK: v{{[0-9]+}}.uw = vabsdiff(v{{[0-9]+}}.w,v{{[0-9]+}}.w)309define <16 x i32> @test39(<16 x i32> %a, <16 x i32> %b) #0 {310entry:311 %0 = tail call <16 x i32> @llvm.hexagon.V6.vabsdiffw(<16 x i32> %a, <16 x i32> %b)312 ret <16 x i32> %0313}314 315; CHECK-LABEL: test40:316; CHECK: v{{[0-9]+}}.ub = vavg(v{{[0-9]+}}.ub,v{{[0-9]+}}.ub)317define <16 x i32> @test40(<16 x i32> %a, <16 x i32> %b) #0 {318entry:319 %0 = tail call <16 x i32> @llvm.hexagon.V6.vavgub(<16 x i32> %a, <16 x i32> %b)320 ret <16 x i32> %0321}322 323; CHECK-LABEL: test41:324; CHECK: v{{[0-9]+}}.uh = vavg(v{{[0-9]+}}.uh,v{{[0-9]+}}.uh)325define <16 x i32> @test41(<16 x i32> %a, <16 x i32> %b) #0 {326entry:327 %0 = tail call <16 x i32> @llvm.hexagon.V6.vavguh(<16 x i32> %a, <16 x i32> %b)328 ret <16 x i32> %0329}330 331; CHECK-LABEL: test42:332; CHECK: v{{[0-9]+}}.h = vavg(v{{[0-9]+}}.h,v{{[0-9]+}}.h)333define <16 x i32> @test42(<16 x i32> %a, <16 x i32> %b) #0 {334entry:335 %0 = tail call <16 x i32> @llvm.hexagon.V6.vavgh(<16 x i32> %a, <16 x i32> %b)336 ret <16 x i32> %0337}338 339; CHECK-LABEL: test43:340; CHECK: v{{[0-9]+}}.w = vavg(v{{[0-9]+}}.w,v{{[0-9]+}}.w)341define <16 x i32> @test43(<16 x i32> %a, <16 x i32> %b) #0 {342entry:343 %0 = tail call <16 x i32> @llvm.hexagon.V6.vavgw(<16 x i32> %a, <16 x i32> %b)344 ret <16 x i32> %0345}346 347; CHECK-LABEL: test44:348; CHECK: v{{[0-9]+}}.b = vnavg(v{{[0-9]+}}.ub,v{{[0-9]+}}.ub)349define <16 x i32> @test44(<16 x i32> %a, <16 x i32> %b) #0 {350entry:351 %0 = tail call <16 x i32> @llvm.hexagon.V6.vnavgub(<16 x i32> %a, <16 x i32> %b)352 ret <16 x i32> %0353}354 355; CHECK-LABEL: test45:356; CHECK: v{{[0-9]+}}.h = vnavg(v{{[0-9]+}}.h,v{{[0-9]+}}.h)357define <16 x i32> @test45(<16 x i32> %a, <16 x i32> %b) #0 {358entry:359 %0 = tail call <16 x i32> @llvm.hexagon.V6.vnavgh(<16 x i32> %a, <16 x i32> %b)360 ret <16 x i32> %0361}362 363; CHECK-LABEL: test46:364; CHECK: v{{[0-9]+}}.w = vnavg(v{{[0-9]+}}.w,v{{[0-9]+}}.w)365define <16 x i32> @test46(<16 x i32> %a, <16 x i32> %b) #0 {366entry:367 %0 = tail call <16 x i32> @llvm.hexagon.V6.vnavgw(<16 x i32> %a, <16 x i32> %b)368 ret <16 x i32> %0369}370 371; CHECK-LABEL: test47:372; CHECK: v{{[0-9]+}}.ub = vavg(v{{[0-9]+}}.ub,v{{[0-9]+}}.ub):rnd373define <16 x i32> @test47(<16 x i32> %a, <16 x i32> %b) #0 {374entry:375 %0 = tail call <16 x i32> @llvm.hexagon.V6.vavgubrnd(<16 x i32> %a, <16 x i32> %b)376 ret <16 x i32> %0377}378 379; CHECK-LABEL: test48:380; CHECK: v{{[0-9]+}}.uh = vavg(v{{[0-9]+}}.uh,v{{[0-9]+}}.uh):rnd381define <16 x i32> @test48(<16 x i32> %a, <16 x i32> %b) #0 {382entry:383 %0 = tail call <16 x i32> @llvm.hexagon.V6.vavguhrnd(<16 x i32> %a, <16 x i32> %b)384 ret <16 x i32> %0385}386 387; CHECK-LABEL: test49:388; CHECK: v{{[0-9]+}}.h = vavg(v{{[0-9]+}}.h,v{{[0-9]+}}.h):rnd389define <16 x i32> @test49(<16 x i32> %a, <16 x i32> %b) #0 {390entry:391 %0 = tail call <16 x i32> @llvm.hexagon.V6.vavghrnd(<16 x i32> %a, <16 x i32> %b)392 ret <16 x i32> %0393}394 395; CHECK-LABEL: test50:396; CHECK: v{{[0-9]+}}.w = vavg(v{{[0-9]+}}.w,v{{[0-9]+}}.w):rnd397define <16 x i32> @test50(<16 x i32> %a, <16 x i32> %b) #0 {398entry:399 %0 = tail call <16 x i32> @llvm.hexagon.V6.vavgwrnd(<16 x i32> %a, <16 x i32> %b)400 ret <16 x i32> %0401}402 403; CHECK-LABEL: test51:404; CHECK: v{{[0-9]+}}:{{[0-9]+}}.h = vmpa(v{{[0-9]+}}:{{[0-9]+}}.ub,v{{[0-9]+}}:{{[0-9]+}}.ub)405define <32 x i32> @test51(<32 x i32> %a, <32 x i32> %b) #0 {406entry:407 %0 = tail call <32 x i32> @llvm.hexagon.V6.vmpabuuv(<32 x i32> %a, <32 x i32> %b)408 ret <32 x i32> %0409}410 411; CHECK-LABEL: test52:412; CHECK: v{{[0-9]+}}.ub = vmin(v{{[0-9]+}}.ub,v{{[0-9]+}}.ub)413define <16 x i32> @test52(<16 x i32> %a, <16 x i32> %b) #0 {414entry:415 %0 = tail call <16 x i32> @llvm.hexagon.V6.vminub(<16 x i32> %a, <16 x i32> %b)416 ret <16 x i32> %0417}418 419; CHECK-LABEL: test53:420; CHECK: v{{[0-9]+}}.uh = vmin(v{{[0-9]+}}.uh,v{{[0-9]+}}.uh)421define <16 x i32> @test53(<16 x i32> %a, <16 x i32> %b) #0 {422entry:423 %0 = tail call <16 x i32> @llvm.hexagon.V6.vminuh(<16 x i32> %a, <16 x i32> %b)424 ret <16 x i32> %0425}426 427; CHECK-LABEL: test54:428; CHECK: v{{[0-9]+}}.h = vmin(v{{[0-9]+}}.h,v{{[0-9]+}}.h)429define <16 x i32> @test54(<16 x i32> %a, <16 x i32> %b) #0 {430entry:431 %0 = tail call <16 x i32> @llvm.hexagon.V6.vminh(<16 x i32> %a, <16 x i32> %b)432 ret <16 x i32> %0433}434 435; CHECK-LABEL: test55:436; CHECK: v{{[0-9]+}}.w = vmin(v{{[0-9]+}}.w,v{{[0-9]+}}.w)437define <16 x i32> @test55(<16 x i32> %a, <16 x i32> %b) #0 {438entry:439 %0 = tail call <16 x i32> @llvm.hexagon.V6.vminw(<16 x i32> %a, <16 x i32> %b)440 ret <16 x i32> %0441}442 443; CHECK-LABEL: test56:444; CHECK: v{{[0-9]+}}.ub = vmax(v{{[0-9]+}}.ub,v{{[0-9]+}}.ub)445define <16 x i32> @test56(<16 x i32> %a, <16 x i32> %b) #0 {446entry:447 %0 = tail call <16 x i32> @llvm.hexagon.V6.vmaxub(<16 x i32> %a, <16 x i32> %b)448 ret <16 x i32> %0449}450 451; CHECK-LABEL: test57:452; CHECK: v{{[0-9]+}}.uh = vmax(v{{[0-9]+}}.uh,v{{[0-9]+}}.uh)453define <16 x i32> @test57(<16 x i32> %a, <16 x i32> %b) #0 {454entry:455 %0 = tail call <16 x i32> @llvm.hexagon.V6.vmaxuh(<16 x i32> %a, <16 x i32> %b)456 ret <16 x i32> %0457}458 459; CHECK-LABEL: test58:460; CHECK: v{{[0-9]+}}.h = vmax(v{{[0-9]+}}.h,v{{[0-9]+}}.h)461define <16 x i32> @test58(<16 x i32> %a, <16 x i32> %b) #0 {462entry:463 %0 = tail call <16 x i32> @llvm.hexagon.V6.vmaxh(<16 x i32> %a, <16 x i32> %b)464 ret <16 x i32> %0465}466 467; CHECK-LABEL: test59:468; CHECK: v{{[0-9]+}}.w = vmax(v{{[0-9]+}}.w,v{{[0-9]+}}.w)469define <16 x i32> @test59(<16 x i32> %a, <16 x i32> %b) #0 {470entry:471 %0 = tail call <16 x i32> @llvm.hexagon.V6.vmaxw(<16 x i32> %a, <16 x i32> %b)472 ret <16 x i32> %0473}474 475; CHECK-LABEL: test60:476; CHECK: v{{[0-9]+}} = vdelta(v{{[0-9]+}},v{{[0-9]+}})477define <16 x i32> @test60(<16 x i32> %a, <16 x i32> %b) #0 {478entry:479 %0 = tail call <16 x i32> @llvm.hexagon.V6.vdelta(<16 x i32> %a, <16 x i32> %b)480 ret <16 x i32> %0481}482 483; CHECK-LABEL: test61:484; CHECK: v{{[0-9]+}} = vrdelta(v{{[0-9]+}},v{{[0-9]+}})485define <16 x i32> @test61(<16 x i32> %a, <16 x i32> %b) #0 {486entry:487 %0 = tail call <16 x i32> @llvm.hexagon.V6.vrdelta(<16 x i32> %a, <16 x i32> %b)488 ret <16 x i32> %0489}490 491; CHECK-LABEL: test62:492; CHECK: v{{[0-9]+}}.b = vdeale(v{{[0-9]+}}.b,v{{[0-9]+}}.b)493define <16 x i32> @test62(<16 x i32> %a, <16 x i32> %b) #0 {494entry:495 %0 = tail call <16 x i32> @llvm.hexagon.V6.vdealb4w(<16 x i32> %a, <16 x i32> %b)496 ret <16 x i32> %0497}498 499; CHECK-LABEL: test63:500; CHECK: v{{[0-9]+}}.b = vshuffe(v{{[0-9]+}}.b,v{{[0-9]+}}.b)501define <16 x i32> @test63(<16 x i32> %a, <16 x i32> %b) #0 {502entry:503 %0 = tail call <16 x i32> @llvm.hexagon.V6.vshuffeb(<16 x i32> %a, <16 x i32> %b)504 ret <16 x i32> %0505}506 507; CHECK-LABEL: test64:508; CHECK: v{{[0-9]+}}.b = vshuffo(v{{[0-9]+}}.b,v{{[0-9]+}}.b)509define <16 x i32> @test64(<16 x i32> %a, <16 x i32> %b) #0 {510entry:511 %0 = tail call <16 x i32> @llvm.hexagon.V6.vshuffob(<16 x i32> %a, <16 x i32> %b)512 ret <16 x i32> %0513}514 515; CHECK-LABEL: test65:516; CHECK: v{{[0-9]+}}.h = vshuffe(v{{[0-9]+}}.h,v{{[0-9]+}}.h)517define <16 x i32> @test65(<16 x i32> %a, <16 x i32> %b) #0 {518entry:519 %0 = tail call <16 x i32> @llvm.hexagon.V6.vshufeh(<16 x i32> %a, <16 x i32> %b)520 ret <16 x i32> %0521}522 523; CHECK-LABEL: test66:524; CHECK: v{{[0-9]+}}.h = vshuffo(v{{[0-9]+}}.h,v{{[0-9]+}}.h)525define <16 x i32> @test66(<16 x i32> %a, <16 x i32> %b) #0 {526entry:527 %0 = tail call <16 x i32> @llvm.hexagon.V6.vshufoh(<16 x i32> %a, <16 x i32> %b)528 ret <16 x i32> %0529}530 531; CHECK-LABEL: test67:532; CHECK: v{{[0-9]+}}:{{[0-9]+}}.h = vshuffoe(v{{[0-9]+}}.h,v{{[0-9]+}}.h)533define <32 x i32> @test67(<16 x i32> %a, <16 x i32> %b) #0 {534entry:535 %0 = tail call <32 x i32> @llvm.hexagon.V6.vshufoeh(<16 x i32> %a, <16 x i32> %b)536 ret <32 x i32> %0537}538 539; CHECK-LABEL: test68:540; CHECK: v{{[0-9]+}}:{{[0-9]+}}.b = vshuffoe(v{{[0-9]+}}.b,v{{[0-9]+}}.b)541define <32 x i32> @test68(<16 x i32> %a, <16 x i32> %b) #0 {542entry:543 %0 = tail call <32 x i32> @llvm.hexagon.V6.vshufoeb(<16 x i32> %a, <16 x i32> %b)544 ret <32 x i32> %0545}546 547; CHECK-LABEL: test69:548; CHECK: v{{[0-9]+}}:{{[0-9]+}} = vcombine(v{{[0-9]+}},v{{[0-9]+}})549define <32 x i32> @test69(<16 x i32> %a, <16 x i32> %b) #0 {550entry:551 %0 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %a, <16 x i32> %b)552 ret <32 x i32> %0553}554 555; CHECK-LABEL: test70:556; CHECK: v{{[0-9]+}}.ub = vsat(v{{[0-9]+}}.h,v{{[0-9]+}}.h)557define <16 x i32> @test70(<16 x i32> %a, <16 x i32> %b) #0 {558entry:559 %0 = tail call <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32> %a, <16 x i32> %b)560 ret <16 x i32> %0561}562 563; CHECK-LABEL: test71:564; CHECK: v{{[0-9]+}}.h = vsat(v{{[0-9]+}}.w,v{{[0-9]+}}.w)565define <16 x i32> @test71(<16 x i32> %a, <16 x i32> %b) #0 {566entry:567 %0 = tail call <16 x i32> @llvm.hexagon.V6.vsatwh(<16 x i32> %a, <16 x i32> %b)568 ret <16 x i32> %0569}570 571; CHECK-LABEL: test72:572; CHECK: v{{[0-9]+}}.h = vround(v{{[0-9]+}}.w,v{{[0-9]+}}.w):sat573define <16 x i32> @test72(<16 x i32> %a, <16 x i32> %b) #0 {574entry:575 %0 = tail call <16 x i32> @llvm.hexagon.V6.vroundwh(<16 x i32> %a, <16 x i32> %b)576 ret <16 x i32> %0577}578 579; CHECK-LABEL: test73:580; CHECK: v{{[0-9]+}}.uh = vround(v{{[0-9]+}}.w,v{{[0-9]+}}.w):sat581define <16 x i32> @test73(<16 x i32> %a, <16 x i32> %b) #0 {582entry:583 %0 = tail call <16 x i32> @llvm.hexagon.V6.vroundwuh(<16 x i32> %a, <16 x i32> %b)584 ret <16 x i32> %0585}586 587; CHECK-LABEL: test74:588; CHECK: v{{[0-9]+}}.b = vround(v{{[0-9]+}}.h,v{{[0-9]+}}.h):sat589define <16 x i32> @test74(<16 x i32> %a, <16 x i32> %b) #0 {590entry:591 %0 = tail call <16 x i32> @llvm.hexagon.V6.vroundhb(<16 x i32> %a, <16 x i32> %b)592 ret <16 x i32> %0593}594 595; CHECK-LABEL: test75:596; CHECK: v{{[0-9]+}}.ub = vround(v{{[0-9]+}}.h,v{{[0-9]+}}.h):sat597define <16 x i32> @test75(<16 x i32> %a, <16 x i32> %b) #0 {598entry:599 %0 = tail call <16 x i32> @llvm.hexagon.V6.vroundhub(<16 x i32> %a, <16 x i32> %b)600 ret <16 x i32> %0601}602 603; CHECK-LABEL: test76:604; CHECK: v{{[0-9]+}}.w = vasr(v{{[0-9]+}}.w,v{{[0-9]+}}.w)605define <16 x i32> @test76(<16 x i32> %a, <16 x i32> %b) #0 {606entry:607 %0 = tail call <16 x i32> @llvm.hexagon.V6.vasrwv(<16 x i32> %a, <16 x i32> %b)608 ret <16 x i32> %0609}610 611; CHECK-LABEL: test77:612; CHECK: v{{[0-9]+}}.w = vlsr(v{{[0-9]+}}.w,v{{[0-9]+}}.w)613define <16 x i32> @test77(<16 x i32> %a, <16 x i32> %b) #0 {614entry:615 %0 = tail call <16 x i32> @llvm.hexagon.V6.vlsrwv(<16 x i32> %a, <16 x i32> %b)616 ret <16 x i32> %0617}618 619; CHECK-LABEL: test78:620; CHECK: v{{[0-9]+}}.h = vlsr(v{{[0-9]+}}.h,v{{[0-9]+}}.h)621define <16 x i32> @test78(<16 x i32> %a, <16 x i32> %b) #0 {622entry:623 %0 = tail call <16 x i32> @llvm.hexagon.V6.vlsrhv(<16 x i32> %a, <16 x i32> %b)624 ret <16 x i32> %0625}626 627; CHECK-LABEL: test79:628; CHECK: v{{[0-9]+}}.h = vasr(v{{[0-9]+}}.h,v{{[0-9]+}}.h)629define <16 x i32> @test79(<16 x i32> %a, <16 x i32> %b) #0 {630entry:631 %0 = tail call <16 x i32> @llvm.hexagon.V6.vasrhv(<16 x i32> %a, <16 x i32> %b)632 ret <16 x i32> %0633}634 635; CHECK-LABEL: test80:636; CHECK: v{{[0-9]+}}.w = vasl(v{{[0-9]+}}.w,v{{[0-9]+}}.w)637define <16 x i32> @test80(<16 x i32> %a, <16 x i32> %b) #0 {638entry:639 %0 = tail call <16 x i32> @llvm.hexagon.V6.vaslwv(<16 x i32> %a, <16 x i32> %b)640 ret <16 x i32> %0641}642 643; CHECK-LABEL: test81:644; CHECK: v{{[0-9]+}}.h = vasl(v{{[0-9]+}}.h,v{{[0-9]+}}.h)645define <16 x i32> @test81(<16 x i32> %a, <16 x i32> %b) #0 {646entry:647 %0 = tail call <16 x i32> @llvm.hexagon.V6.vaslhv(<16 x i32> %a, <16 x i32> %b)648 ret <16 x i32> %0649}650 651; CHECK-LABEL: test82:652; CHECK: v{{[0-9]+}}.b = vadd(v{{[0-9]+}}.b,v{{[0-9]+}}.b)653define <16 x i32> @test82(<16 x i32> %a, <16 x i32> %b) #0 {654entry:655 %0 = tail call <16 x i32> @llvm.hexagon.V6.vaddb(<16 x i32> %a, <16 x i32> %b)656 ret <16 x i32> %0657}658 659; CHECK-LABEL: test83:660; CHECK: v{{[0-9]+}}.h = vadd(v{{[0-9]+}}.h,v{{[0-9]+}}.h)661define <16 x i32> @test83(<16 x i32> %a, <16 x i32> %b) #0 {662entry:663 %0 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %a, <16 x i32> %b)664 ret <16 x i32> %0665}666 667; CHECK-LABEL: test84:668; CHECK: if (q{{[0-3]}}) v{{[0-9]+}}.b += v{{[0-9]+}}.b669define <16 x i32> @test84(<16 x i32> %a, <16 x i32> %b, <16 x i32> %c) #0 {670entry:671 %0 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a, i32 -1)672 %1 = tail call <16 x i32> @llvm.hexagon.V6.vaddbq(<64 x i1> %0, <16 x i32> %c, <16 x i32> %b)673 ret <16 x i32> %1674}675 676; CHECK-LABEL: test85:677; CHECK: if (q{{[0-3]}}) v{{[0-9]+}}.h += v{{[0-9]+}}.h678define <16 x i32> @test85(<16 x i32> %a, <16 x i32> %b, <16 x i32> %c) #0 {679entry:680 %0 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a, i32 -1)681 %1 = tail call <16 x i32> @llvm.hexagon.V6.vaddhq(<64 x i1> %0, <16 x i32> %c, <16 x i32> %b)682 ret <16 x i32> %1683}684 685; CHECK-LABEL: test86:686; CHECK: if (q{{[0-3]}}) v{{[0-9]+}}.w += v{{[0-9]+}}.w687define <16 x i32> @test86(<16 x i32> %a, <16 x i32> %b, <16 x i32> %c) #0 {688entry:689 %0 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a, i32 -1)690 %1 = tail call <16 x i32> @llvm.hexagon.V6.vaddwq(<64 x i1> %0, <16 x i32> %c, <16 x i32> %b)691 ret <16 x i32> %1692}693 694; CHECK-LABEL: test87:695; CHECK: if (!q{{[0-3]}}) v{{[0-9]+}}.b += v{{[0-9]+}}.b696define <16 x i32> @test87(<16 x i32> %a, <16 x i32> %b, <16 x i32> %c) #0 {697entry:698 %0 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a, i32 -1)699 %1 = tail call <16 x i32> @llvm.hexagon.V6.vaddbnq(<64 x i1> %0, <16 x i32> %c, <16 x i32> %b)700 ret <16 x i32> %1701}702 703; CHECK-LABEL: test88:704; CHECK: if (!q{{[0-3]}}) v{{[0-9]+}}.h += v{{[0-9]+}}.h705define <16 x i32> @test88(<16 x i32> %a, <16 x i32> %b, <16 x i32> %c) #0 {706entry:707 %0 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a, i32 -1)708 %1 = tail call <16 x i32> @llvm.hexagon.V6.vaddhnq(<64 x i1> %0, <16 x i32> %c, <16 x i32> %b)709 ret <16 x i32> %1710}711 712; CHECK-LABEL: test89:713; CHECK: if (!q{{[0-3]}}) v{{[0-9]+}}.w += v{{[0-9]+}}.w714define <16 x i32> @test89(<16 x i32> %a, <16 x i32> %b, <16 x i32> %c) #0 {715entry:716 %0 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a, i32 -1)717 %1 = tail call <16 x i32> @llvm.hexagon.V6.vaddwnq(<64 x i1> %0, <16 x i32> %c, <16 x i32> %b)718 ret <16 x i32> %1719}720 721; CHECK-LABEL: test90:722; CHECK: if (q{{[0-3]}}) v{{[0-9]+}}.b -= v{{[0-9]+}}.b723define <16 x i32> @test90(<16 x i32> %a, <16 x i32> %b, <16 x i32> %c) #0 {724entry:725 %0 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a, i32 -1)726 %1 = tail call <16 x i32> @llvm.hexagon.V6.vsubbq(<64 x i1> %0, <16 x i32> %c, <16 x i32> %b)727 ret <16 x i32> %1728}729 730; CHECK-LABEL: test91:731; CHECK: if (q{{[0-3]}}) v{{[0-9]+}}.h -= v{{[0-9]+}}.h732define <16 x i32> @test91(<16 x i32> %a, <16 x i32> %b, <16 x i32> %c) #0 {733entry:734 %0 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a, i32 -1)735 %1 = tail call <16 x i32> @llvm.hexagon.V6.vsubhq(<64 x i1> %0, <16 x i32> %c, <16 x i32> %b)736 ret <16 x i32> %1737}738 739; CHECK-LABEL: test92:740; CHECK: if (q{{[0-3]}}) v{{[0-9]+}}.w -= v{{[0-9]+}}.w741define <16 x i32> @test92(<16 x i32> %a, <16 x i32> %b, <16 x i32> %c) #0 {742entry:743 %0 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a, i32 -1)744 %1 = tail call <16 x i32> @llvm.hexagon.V6.vsubwq(<64 x i1> %0, <16 x i32> %c, <16 x i32> %b)745 ret <16 x i32> %1746}747 748; CHECK-LABEL: test93:749; CHECK: if (!q{{[0-3]}}) v{{[0-9]+}}.b -= v{{[0-9]+}}.b750define <16 x i32> @test93(<16 x i32> %a, <16 x i32> %b, <16 x i32> %c) #0 {751entry:752 %0 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a, i32 -1)753 %1 = tail call <16 x i32> @llvm.hexagon.V6.vsubbnq(<64 x i1> %0, <16 x i32> %c, <16 x i32> %b)754 ret <16 x i32> %1755}756 757; CHECK-LABEL: test94:758; CHECK: if (!q{{[0-3]}}) v{{[0-9]+}}.h -= v{{[0-9]+}}.h759define <16 x i32> @test94(<16 x i32> %a, <16 x i32> %b, <16 x i32> %c) #0 {760entry:761 %0 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a, i32 -1)762 %1 = tail call <16 x i32> @llvm.hexagon.V6.vsubhnq(<64 x i1> %0, <16 x i32> %c, <16 x i32> %b)763 ret <16 x i32> %1764}765 766; CHECK-LABEL: test95:767; CHECK: if (!q{{[0-3]}}) v{{[0-9]+}}.w -= v{{[0-9]+}}.w768define <16 x i32> @test95(<16 x i32> %a, <16 x i32> %b, <16 x i32> %c) #0 {769entry:770 %0 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a, i32 -1)771 %1 = tail call <16 x i32> @llvm.hexagon.V6.vsubwnq(<64 x i1> %0, <16 x i32> %c, <16 x i32> %b)772 ret <16 x i32> %1773}774 775; CHECK-LABEL: test96:776; CHECK: v{{[0-9]+}}.h = vabs(v{{[0-9]+}}.h)777define <16 x i32> @test96(<16 x i32> %a) #0 {778entry:779 %0 = tail call <16 x i32> @llvm.hexagon.V6.vabsh(<16 x i32> %a)780 ret <16 x i32> %0781}782 783; CHECK-LABEL: test97:784; CHECK: v{{[0-9]+}}.h = vabs(v{{[0-9]+}}.h):sat785define <16 x i32> @test97(<16 x i32> %a) #0 {786entry:787 %0 = tail call <16 x i32> @llvm.hexagon.V6.vabsh.sat(<16 x i32> %a)788 ret <16 x i32> %0789}790 791; CHECK-LABEL: test98:792; CHECK: v{{[0-9]+}}.w = vabs(v{{[0-9]+}}.w)793define <16 x i32> @test98(<16 x i32> %a) #0 {794entry:795 %0 = tail call <16 x i32> @llvm.hexagon.V6.vabsw(<16 x i32> %a)796 ret <16 x i32> %0797}798 799; CHECK-LABEL: test99:800; CHECK: v{{[0-9]+}}.w = vabs(v{{[0-9]+}}.w):sat801define <16 x i32> @test99(<16 x i32> %a) #0 {802entry:803 %0 = tail call <16 x i32> @llvm.hexagon.V6.vabsw.sat(<16 x i32> %a)804 ret <16 x i32> %0805}806 807; CHECK-LABEL: test100:808; CHECK: v{{[0-9]+}} = vnot(v{{[0-9]+}})809define <16 x i32> @test100(<16 x i32> %a) #0 {810entry:811 %0 = tail call <16 x i32> @llvm.hexagon.V6.vnot(<16 x i32> %a)812 ret <16 x i32> %0813}814 815; CHECK-LABEL: test101:816; CHECK: v{{[0-9]+}}.h = vdeal(v{{[0-9]+}}.h)817define <16 x i32> @test101(<16 x i32> %a) #0 {818entry:819 %0 = tail call <16 x i32> @llvm.hexagon.V6.vdealh(<16 x i32> %a)820 ret <16 x i32> %0821}822 823; CHECK-LABEL: test102:824; CHECK: v{{[0-9]+}}.b = vdeal(v{{[0-9]+}}.b)825define <16 x i32> @test102(<16 x i32> %a) #0 {826entry:827 %0 = tail call <16 x i32> @llvm.hexagon.V6.vdealb(<16 x i32> %a)828 ret <16 x i32> %0829}830 831; CHECK-LABEL: test103:832; CHECK: v{{[0-9]+}}:{{[0-9]+}}.uh = vunpack(v{{[0-9]+}}.ub)833define <32 x i32> @test103(<16 x i32> %a) #0 {834entry:835 %0 = tail call <32 x i32> @llvm.hexagon.V6.vunpackub(<16 x i32> %a)836 ret <32 x i32> %0837}838 839; CHECK-LABEL: test104:840; CHECK: v{{[0-9]+}}:{{[0-9]+}}.uw = vunpack(v{{[0-9]+}}.uh)841define <32 x i32> @test104(<16 x i32> %a) #0 {842entry:843 %0 = tail call <32 x i32> @llvm.hexagon.V6.vunpackuh(<16 x i32> %a)844 ret <32 x i32> %0845}846 847; CHECK-LABEL: test105:848; CHECK: v{{[0-9]+}}:{{[0-9]+}}.h = vunpack(v{{[0-9]+}}.b)849define <32 x i32> @test105(<16 x i32> %a) #0 {850entry:851 %0 = tail call <32 x i32> @llvm.hexagon.V6.vunpackb(<16 x i32> %a)852 ret <32 x i32> %0853}854 855; CHECK-LABEL: test106:856; CHECK: v{{[0-9]+}}:{{[0-9]+}}.w = vunpack(v{{[0-9]+}}.h)857define <32 x i32> @test106(<16 x i32> %a) #0 {858entry:859 %0 = tail call <32 x i32> @llvm.hexagon.V6.vunpackh(<16 x i32> %a)860 ret <32 x i32> %0861}862 863; CHECK-LABEL: test107:864; CHECK: v{{[0-9]+}}.h = vshuff(v{{[0-9]+}}.h)865define <16 x i32> @test107(<16 x i32> %a) #0 {866entry:867 %0 = tail call <16 x i32> @llvm.hexagon.V6.vshuffh(<16 x i32> %a)868 ret <16 x i32> %0869}870 871; CHECK-LABEL: test108:872; CHECK: v{{[0-9]+}}.b = vshuff(v{{[0-9]+}}.b)873define <16 x i32> @test108(<16 x i32> %a) #0 {874entry:875 %0 = tail call <16 x i32> @llvm.hexagon.V6.vshuffb(<16 x i32> %a)876 ret <16 x i32> %0877}878 879; CHECK-LABEL: test109:880; CHECK: v{{[0-9]+}}:{{[0-9]+}}.uh = vzxt(v{{[0-9]+}}.ub)881define <32 x i32> @test109(<16 x i32> %a) #0 {882entry:883 %0 = tail call <32 x i32> @llvm.hexagon.V6.vzb(<16 x i32> %a)884 ret <32 x i32> %0885}886 887; CHECK-LABEL: test110:888; CHECK: v{{[0-9]+}}:{{[0-9]+}}.uw = vzxt(v{{[0-9]+}}.uh)889define <32 x i32> @test110(<16 x i32> %a) #0 {890entry:891 %0 = tail call <32 x i32> @llvm.hexagon.V6.vzh(<16 x i32> %a)892 ret <32 x i32> %0893}894 895; CHECK-LABEL: test111:896; CHECK: v{{[0-9]+}}:{{[0-9]+}}.h = vsxt(v{{[0-9]+}}.b)897define <32 x i32> @test111(<16 x i32> %a) #0 {898entry:899 %0 = tail call <32 x i32> @llvm.hexagon.V6.vsb(<16 x i32> %a)900 ret <32 x i32> %0901}902 903; CHECK-LABEL: test112:904; CHECK: v{{[0-9]+}}:{{[0-9]+}}.w = vsxt(v{{[0-9]+}}.h)905define <32 x i32> @test112(<16 x i32> %a) #0 {906entry:907 %0 = tail call <32 x i32> @llvm.hexagon.V6.vsh(<16 x i32> %a)908 ret <32 x i32> %0909}910 911; CHECK-LABEL: test113:912; CHECK: v{{[0-9]+}} = v{{[0-9]+}}913define <16 x i32> @test113(<16 x i32> %a) #0 {914entry:915 %0 = tail call <16 x i32> @llvm.hexagon.V6.vassign(<16 x i32> %a)916 ret <16 x i32> %0917}918 919declare <16 x i32> @llvm.hexagon.V6.vadduhsat(<16 x i32>, <16 x i32>) #0920declare <16 x i32> @llvm.hexagon.V6.vaddhsat(<16 x i32>, <16 x i32>) #0921declare <16 x i32> @llvm.hexagon.V6.vaddwsat(<16 x i32>, <16 x i32>) #0922declare <16 x i32> @llvm.hexagon.V6.vsubb(<16 x i32>, <16 x i32>) #0923declare <16 x i32> @llvm.hexagon.V6.vsubh(<16 x i32>, <16 x i32>) #0924declare <16 x i32> @llvm.hexagon.V6.vsubw(<16 x i32>, <16 x i32>) #0925declare <16 x i32> @llvm.hexagon.V6.vsububsat(<16 x i32>, <16 x i32>) #0926declare <16 x i32> @llvm.hexagon.V6.vsubuhsat(<16 x i32>, <16 x i32>) #0927declare <16 x i32> @llvm.hexagon.V6.vsubhsat(<16 x i32>, <16 x i32>) #0928declare <16 x i32> @llvm.hexagon.V6.vsubwsat(<16 x i32>, <16 x i32>) #0929declare <32 x i32> @llvm.hexagon.V6.vaddb.dv(<32 x i32>, <32 x i32>) #0930declare <32 x i32> @llvm.hexagon.V6.vaddh.dv(<32 x i32>, <32 x i32>) #0931declare <32 x i32> @llvm.hexagon.V6.vaddw.dv(<32 x i32>, <32 x i32>) #0932declare <32 x i32> @llvm.hexagon.V6.vaddubsat.dv(<32 x i32>, <32 x i32>) #0933declare <32 x i32> @llvm.hexagon.V6.vadduhsat.dv(<32 x i32>, <32 x i32>) #0934declare <32 x i32> @llvm.hexagon.V6.vaddhsat.dv(<32 x i32>, <32 x i32>) #0935declare <32 x i32> @llvm.hexagon.V6.vaddwsat.dv(<32 x i32>, <32 x i32>) #0936declare <32 x i32> @llvm.hexagon.V6.vsubb.dv(<32 x i32>, <32 x i32>) #0937declare <32 x i32> @llvm.hexagon.V6.vsubh.dv(<32 x i32>, <32 x i32>) #0938declare <32 x i32> @llvm.hexagon.V6.vsubw.dv(<32 x i32>, <32 x i32>) #0939declare <32 x i32> @llvm.hexagon.V6.vsububsat.dv(<32 x i32>, <32 x i32>) #0940declare <32 x i32> @llvm.hexagon.V6.vsubuhsat.dv(<32 x i32>, <32 x i32>) #0941declare <32 x i32> @llvm.hexagon.V6.vsubhsat.dv(<32 x i32>, <32 x i32>) #0942declare <32 x i32> @llvm.hexagon.V6.vsubwsat.dv(<32 x i32>, <32 x i32>) #0943declare <32 x i32> @llvm.hexagon.V6.vaddubh(<16 x i32>, <16 x i32>) #0944declare <32 x i32> @llvm.hexagon.V6.vadduhw(<16 x i32>, <16 x i32>) #0945declare <32 x i32> @llvm.hexagon.V6.vaddhw(<16 x i32>, <16 x i32>) #0946declare <32 x i32> @llvm.hexagon.V6.vsububh(<16 x i32>, <16 x i32>) #0947declare <32 x i32> @llvm.hexagon.V6.vsubuhw(<16 x i32>, <16 x i32>) #0948declare <32 x i32> @llvm.hexagon.V6.vsubhw(<16 x i32>, <16 x i32>) #0949declare <16 x i32> @llvm.hexagon.V6.vabsdiffub(<16 x i32>, <16 x i32>) #0950declare <16 x i32> @llvm.hexagon.V6.vabsdiffh(<16 x i32>, <16 x i32>) #0951declare <16 x i32> @llvm.hexagon.V6.vabsdiffuh(<16 x i32>, <16 x i32>) #0952declare <16 x i32> @llvm.hexagon.V6.vabsdiffw(<16 x i32>, <16 x i32>) #0953declare <16 x i32> @llvm.hexagon.V6.vavgub(<16 x i32>, <16 x i32>) #0954declare <16 x i32> @llvm.hexagon.V6.vavguh(<16 x i32>, <16 x i32>) #0955declare <16 x i32> @llvm.hexagon.V6.vavgh(<16 x i32>, <16 x i32>) #0956declare <16 x i32> @llvm.hexagon.V6.vavgw(<16 x i32>, <16 x i32>) #0957declare <16 x i32> @llvm.hexagon.V6.vnavgub(<16 x i32>, <16 x i32>) #0958declare <16 x i32> @llvm.hexagon.V6.vnavgh(<16 x i32>, <16 x i32>) #0959declare <16 x i32> @llvm.hexagon.V6.vnavgw(<16 x i32>, <16 x i32>) #0960declare <16 x i32> @llvm.hexagon.V6.vavgubrnd(<16 x i32>, <16 x i32>) #0961declare <16 x i32> @llvm.hexagon.V6.vavghrnd(<16 x i32>, <16 x i32>) #0962declare <16 x i32> @llvm.hexagon.V6.vavguhrnd(<16 x i32>, <16 x i32>) #0963declare <16 x i32> @llvm.hexagon.V6.vavgwrnd(<16 x i32>, <16 x i32>) #0964declare <32 x i32> @llvm.hexagon.V6.vmpabuuv(<32 x i32>, <32 x i32>) #0965declare <16 x i32> @llvm.hexagon.V6.vand(<16 x i32>, <16 x i32>) #0966declare <16 x i32> @llvm.hexagon.V6.vminub(<16 x i32>, <16 x i32>) #0967declare <16 x i32> @llvm.hexagon.V6.vminuh(<16 x i32>, <16 x i32>) #0968declare <16 x i32> @llvm.hexagon.V6.vminh(<16 x i32>, <16 x i32>) #0969declare <16 x i32> @llvm.hexagon.V6.vminw(<16 x i32>, <16 x i32>) #0970declare <16 x i32> @llvm.hexagon.V6.vmaxub(<16 x i32>, <16 x i32>) #0971declare <16 x i32> @llvm.hexagon.V6.vmaxuh(<16 x i32>, <16 x i32>) #0972declare <16 x i32> @llvm.hexagon.V6.vmaxh(<16 x i32>, <16 x i32>) #0973declare <16 x i32> @llvm.hexagon.V6.vmaxw(<16 x i32>, <16 x i32>) #0974declare <16 x i32> @llvm.hexagon.V6.vdelta(<16 x i32>, <16 x i32>) #0975declare <16 x i32> @llvm.hexagon.V6.vrdelta(<16 x i32>, <16 x i32>) #0976declare <16 x i32> @llvm.hexagon.V6.vdealb4w(<16 x i32>, <16 x i32>) #0977declare <16 x i32> @llvm.hexagon.V6.vshuffob(<16 x i32>, <16 x i32>) #0978declare <16 x i32> @llvm.hexagon.V6.vshuffeb(<16 x i32>, <16 x i32>) #0979declare <16 x i32> @llvm.hexagon.V6.vshufeh(<16 x i32>, <16 x i32>) #0980declare <16 x i32> @llvm.hexagon.V6.vshufoh(<16 x i32>, <16 x i32>) #0981declare <32 x i32> @llvm.hexagon.V6.vshufoeh(<16 x i32>, <16 x i32>) #0982declare <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32>, <16 x i32>) #0983declare <32 x i32> @llvm.hexagon.V6.vshufoeb(<16 x i32>, <16 x i32>) #0984declare <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32>, <16 x i32>) #0985declare <16 x i32> @llvm.hexagon.V6.vsatwh(<16 x i32>, <16 x i32>) #0986declare <16 x i32> @llvm.hexagon.V6.vroundwh(<16 x i32>, <16 x i32>) #0987declare <16 x i32> @llvm.hexagon.V6.vroundhb(<16 x i32>, <16 x i32>) #0988declare <16 x i32> @llvm.hexagon.V6.vroundwuh(<16 x i32>, <16 x i32>) #0989declare <16 x i32> @llvm.hexagon.V6.vroundhub(<16 x i32>, <16 x i32>) #0990declare <16 x i32> @llvm.hexagon.V6.vasrwv(<16 x i32>, <16 x i32>) #0991declare <16 x i32> @llvm.hexagon.V6.vlsrwv(<16 x i32>, <16 x i32>) #0992declare <16 x i32> @llvm.hexagon.V6.vasrhv(<16 x i32>, <16 x i32>) #0993declare <16 x i32> @llvm.hexagon.V6.vlsrhv(<16 x i32>, <16 x i32>) #0994declare <16 x i32> @llvm.hexagon.V6.vaslwv(<16 x i32>, <16 x i32>) #0995declare <16 x i32> @llvm.hexagon.V6.vaslhv(<16 x i32>, <16 x i32>) #0996declare <16 x i32> @llvm.hexagon.V6.vaddb(<16 x i32>, <16 x i32>) #0997declare <16 x i32> @llvm.hexagon.V6.vor(<16 x i32>, <16 x i32>) #0998declare <16 x i32> @llvm.hexagon.V6.vxor(<16 x i32>, <16 x i32>) #0999declare <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32>, <16 x i32>) #01000declare <16 x i32> @llvm.hexagon.V6.vaddubsat(<16 x i32>, <16 x i32>) #01001declare <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32>, <16 x i32>) #01002declare <16 x i32> @llvm.hexagon.V6.vaddbq(<64 x i1>, <16 x i32>, <16 x i32>) #01003declare <16 x i32> @llvm.hexagon.V6.vaddhq(<64 x i1>, <16 x i32>, <16 x i32>) #01004declare <16 x i32> @llvm.hexagon.V6.vaddwq(<64 x i1>, <16 x i32>, <16 x i32>) #01005declare <16 x i32> @llvm.hexagon.V6.vaddbnq(<64 x i1>, <16 x i32>, <16 x i32>) #01006declare <16 x i32> @llvm.hexagon.V6.vaddhnq(<64 x i1>, <16 x i32>, <16 x i32>) #01007declare <16 x i32> @llvm.hexagon.V6.vaddwnq(<64 x i1>, <16 x i32>, <16 x i32>) #01008declare <16 x i32> @llvm.hexagon.V6.vsubbq(<64 x i1>, <16 x i32>, <16 x i32>) #01009declare <16 x i32> @llvm.hexagon.V6.vsubhq(<64 x i1>, <16 x i32>, <16 x i32>) #01010declare <16 x i32> @llvm.hexagon.V6.vsubwq(<64 x i1>, <16 x i32>, <16 x i32>) #01011declare <16 x i32> @llvm.hexagon.V6.vsubbnq(<64 x i1>, <16 x i32>, <16 x i32>) #01012declare <16 x i32> @llvm.hexagon.V6.vsubhnq(<64 x i1>, <16 x i32>, <16 x i32>) #01013declare <16 x i32> @llvm.hexagon.V6.vsubwnq(<64 x i1>, <16 x i32>, <16 x i32>) #01014declare <16 x i32> @llvm.hexagon.V6.vabsh(<16 x i32>) #01015declare <16 x i32> @llvm.hexagon.V6.vabsh.sat(<16 x i32>) #01016declare <16 x i32> @llvm.hexagon.V6.vabsw(<16 x i32>) #01017declare <16 x i32> @llvm.hexagon.V6.vabsw.sat(<16 x i32>) #01018declare <16 x i32> @llvm.hexagon.V6.vnot(<16 x i32>) #01019declare <16 x i32> @llvm.hexagon.V6.vdealh(<16 x i32>) #01020declare <16 x i32> @llvm.hexagon.V6.vdealb(<16 x i32>) #01021declare <32 x i32> @llvm.hexagon.V6.vunpackub(<16 x i32>) #01022declare <32 x i32> @llvm.hexagon.V6.vunpackuh(<16 x i32>) #01023declare <32 x i32> @llvm.hexagon.V6.vunpackb(<16 x i32>) #01024declare <32 x i32> @llvm.hexagon.V6.vunpackh(<16 x i32>) #01025declare <16 x i32> @llvm.hexagon.V6.vshuffh(<16 x i32>) #01026declare <16 x i32> @llvm.hexagon.V6.vshuffb(<16 x i32>) #01027declare <32 x i32> @llvm.hexagon.V6.vzb(<16 x i32>) #01028declare <32 x i32> @llvm.hexagon.V6.vzh(<16 x i32>) #01029declare <32 x i32> @llvm.hexagon.V6.vsb(<16 x i32>) #01030declare <32 x i32> @llvm.hexagon.V6.vsh(<16 x i32>) #01031declare <16 x i32> @llvm.hexagon.V6.vassign(<16 x i32>) #01032declare <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32>, i32) #01033 1034attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }1035 1036