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1; RUN: llc -mtriple=hexagon < %s | FileCheck %s2 3@l = external global <32 x i32>4@k = external global <16 x i32>5@h = external global <16 x i32>6@n = external global i647@m = external global i328 9; CHECK-LABEL: test1:10; CHECK: v{{[0-9]+}}:{{[0-9]+}}.w = vrmpy(v{{[0-9]+}}:{{[0-9]+}}.ub,r{{[0-9]+}}.b,#1)11define void @test1(<32 x i32> %a, i32 %b) #0 {12entry:13 %0 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi(<32 x i32> %a, i32 %b, i32 1)14 store <32 x i32> %0, ptr @l, align 12815 ret void16}17 18; CHECK-LABEL: test2:19; CHECK: v{{[0-9]+}}:{{[0-9]+}}.uw = vrsad(v{{[0-9]+}}:{{[0-9]+}}.ub,r{{[0-9]+}}.ub,#1)20define void @test2(<32 x i32> %a, i32 %b) #0 {21entry:22 %0 = tail call <32 x i32> @llvm.hexagon.V6.vrsadubi(<32 x i32> %a, i32 %b, i32 1)23 store <32 x i32> %0, ptr @l, align 12824 ret void25}26 27; CHECK-LABEL: test3:28; CHECK: v{{[0-9]+}}:{{[0-9]+}}.uw = vrmpy(v{{[0-9]+}}:{{[0-9]+}}.ub,r{{[0-9]+}}.ub,#1)29define void @test3(<32 x i32> %a, i32 %b) #0 {30entry:31 %0 = tail call <32 x i32> @llvm.hexagon.V6.vrmpyubi(<32 x i32> %a, i32 %b, i32 1)32 store <32 x i32> %0, ptr @l, align 12833 ret void34}35 36; CHECK-LABEL: test4:37; CHECK: v{{[0-9]+}}:{{[0-9]+}}.w += vrmpy(v{{[0-9]+}}:{{[0-9]+}}.ub,r{{[0-9]+}}.b,#1)38define void @test4(<32 x i32> %a, <32 x i32> %b, i32 %c) #0 {39entry:40 %0 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %a, <32 x i32> %b, i32 %c, i32 1)41 store <32 x i32> %0, ptr @l, align 12842 ret void43}44 45; CHECK-LABEL: test5:46; CHECK: v{{[0-9]+}}:{{[0-9]+}}.uw += vrsad(v{{[0-9]+}}:{{[0-9]+}}.ub,r{{[0-9]+}}.ub,#1)47define void @test5(<32 x i32> %a, <32 x i32> %b, i32 %c) #0 {48entry:49 %0 = tail call <32 x i32> @llvm.hexagon.V6.vrsadubi.acc(<32 x i32> %a, <32 x i32> %b, i32 %c, i32 1)50 store <32 x i32> %0, ptr @l, align 12851 ret void52}53 54; CHECK-LABEL: test6:55; CHECK: v{{[0-9]+}}:{{[0-9]+}}.uw += vrmpy(v{{[0-9]+}}:{{[0-9]+}}.ub,r{{[0-9]+}}.ub,#0)56define void @test6(<32 x i32> %a, <32 x i32> %b, i32 %c) #0 {57entry:58 %0 = tail call <32 x i32> @llvm.hexagon.V6.vrmpyubi.acc(<32 x i32> %a, <32 x i32> %b, i32 %c, i32 0)59 store <32 x i32> %0, ptr @l, align 12860 ret void61}62 63; CHECK-LABEL: test7:64; CHECK: v{{[0-9]+}} = valign(v{{[0-9]+}},v{{[0-9]+}},r{{[0-9]+}})65define void @test7(<16 x i32> %a, <16 x i32> %b, i32 %c) #0 {66entry:67 %0 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %a, <16 x i32> %b, i32 %c)68 store <16 x i32> %0, ptr @k, align 6469 ret void70}71 72; CHECK-LABEL: test8:73; CHECK: v{{[0-9]+}} = vlalign(v{{[0-9]+}},v{{[0-9]+}},r{{[0-9]+}})74define void @test8(<16 x i32> %a, <16 x i32> %b, i32 %c) #0 {75entry:76 %0 = tail call <16 x i32> @llvm.hexagon.V6.vlalignb(<16 x i32> %a, <16 x i32> %b, i32 %c)77 store <16 x i32> %0, ptr @k, align 6478 ret void79}80 81; CHECK-LABEL: test9:82; CHECK: v{{[0-9]+}}.h = vasr(v{{[0-9]+}}.w,v{{[0-9]+}}.w,r{{[0-9]+}})83define void @test9(<16 x i32> %a, <16 x i32> %b, i32 %c) #0 {84entry:85 %0 = tail call <16 x i32> @llvm.hexagon.V6.vasrwh(<16 x i32> %a, <16 x i32> %b, i32 %c)86 store <16 x i32> %0, ptr @k, align 6487 ret void88}89 90; CHECK-LABEL: test10:91; CHECK: v{{[0-9]+}}.h = vasr(v{{[0-9]+}}.w,v{{[0-9]+}}.w,r{{[0-9]+}}):sat92define void @test10(<16 x i32> %a, <16 x i32> %b, i32 %c) #0 {93entry:94 %0 = tail call <16 x i32> @llvm.hexagon.V6.vasrwhsat(<16 x i32> %a, <16 x i32> %b, i32 %c)95 store <16 x i32> %0, ptr @k, align 6496 ret void97}98 99; CHECK-LABEL: test11:100; CHECK: v{{[0-9]+}}.h = vasr(v{{[0-9]+}}.w,v{{[0-9]+}}.w,r{{[0-9]+}}):rnd:sat101define void @test11(<16 x i32> %a, <16 x i32> %b, i32 %c) #0 {102entry:103 %0 = tail call <16 x i32> @llvm.hexagon.V6.vasrwhrndsat(<16 x i32> %a, <16 x i32> %b, i32 %c)104 store <16 x i32> %0, ptr @k, align 64105 ret void106}107 108; CHECK-LABEL: test12:109; CHECK: v{{[0-9]+}}.uh = vasr(v{{[0-9]+}}.w,v{{[0-9]+}}.w,r{{[0-9]+}}):sat110define void @test12(<16 x i32> %a, <16 x i32> %b, i32 %c) #0 {111entry:112 %0 = tail call <16 x i32> @llvm.hexagon.V6.vasrwuhsat(<16 x i32> %a, <16 x i32> %b, i32 %c)113 store <16 x i32> %0, ptr @k, align 64114 ret void115}116 117; CHECK-LABEL: test13:118; CHECK: v{{[0-9]+}}.ub = vasr(v{{[0-9]+}}.h,v{{[0-9]+}}.h,r{{[0-9]+}}):sat119define void @test13(<16 x i32> %a, <16 x i32> %b, i32 %c) #0 {120entry:121 %0 = tail call <16 x i32> @llvm.hexagon.V6.vasrhubsat(<16 x i32> %a, <16 x i32> %b, i32 %c)122 store <16 x i32> %0, ptr @k, align 64123 ret void124}125 126; CHECK-LABEL: test14:127; CHECK: v{{[0-9]+}}.ub = vasr(v{{[0-9]+}}.h,v{{[0-9]+}}.h,r{{[0-9]+}}):rnd:sat128define void @test14(<16 x i32> %a, <16 x i32> %b, i32 %c) #0 {129entry:130 %0 = tail call <16 x i32> @llvm.hexagon.V6.vasrhubrndsat(<16 x i32> %a, <16 x i32> %b, i32 %c)131 store <16 x i32> %0, ptr @k, align 64132 ret void133}134 135; CHECK-LABEL: test15:136; CHECK: v{{[0-9]+}}.b = vasr(v{{[0-9]+}}.h,v{{[0-9]+}}.h,r{{[0-9]+}}):rnd:sat137define void @test15(<16 x i32> %a, <16 x i32> %b, i32 %c) #0 {138entry:139 %0 = tail call <16 x i32> @llvm.hexagon.V6.vasrhbrndsat(<16 x i32> %a, <16 x i32> %b, i32 %c)140 store <16 x i32> %0, ptr @k, align 64141 ret void142}143 144; CHECK-LABEL: test16:145; CHECK: v{{[0-9]+}}:{{[0-9]+}}.h |= vunpacko(v{{[0-9]+}}.b)146define void @test16(<32 x i32> %a, <16 x i32> %b) #0 {147entry:148 %0 = tail call <32 x i32> @llvm.hexagon.V6.vunpackob(<32 x i32> %a, <16 x i32> %b)149 store <32 x i32> %0, ptr @l, align 128150 ret void151}152 153; CHECK-LABEL: test17:154; CHECK: v{{[0-9]+}}:{{[0-9]+}}.w |= vunpacko(v{{[0-9]+}}.h)155define void @test17(<32 x i32> %a, <16 x i32> %b) #0 {156entry:157 %0 = tail call <32 x i32> @llvm.hexagon.V6.vunpackoh(<32 x i32> %a, <16 x i32> %b)158 store <32 x i32> %0, ptr @l, align 128159 ret void160}161 162; CHECK-LABEL: test18:163; CHECK: v{{[0-9]+}} = valign(v{{[0-9]+}},v{{[0-9]+}},#3)164define void @test18(<16 x i32> %a, <16 x i32> %b) #0 {165entry:166 %0 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %a, <16 x i32> %b, i32 3)167 store <16 x i32> %0, ptr @k, align 64168 ret void169}170 171; CHECK-LABEL: test19:172; CHECK: v{{[0-9]+}} = vlalign(v{{[0-9]+}},v{{[0-9]+}},#3)173define void @test19(<16 x i32> %a, <16 x i32> %b) #0 {174entry:175 %0 = tail call <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32> %a, <16 x i32> %b, i32 3)176 store <16 x i32> %0, ptr @k, align 64177 ret void178}179 180; CHECK-LABEL: test20:181; CHECK: v{{[0-9]+}} = vmux(q{{[0-3]+}},v{{[0-9]+}},v{{[0-9]+}})182define void @test20(<16 x i32> %a, <16 x i32> %b, <16 x i32> %c) #0 {183entry:184 %0 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a, i32 -1)185 %1 = tail call <16 x i32> @llvm.hexagon.V6.vmux(<64 x i1> %0, <16 x i32> %b, <16 x i32> %c)186 store <16 x i32> %1, ptr @k, align 64187 ret void188}189 190; CHECK-LABEL: test21:191; CHECK: q{{[0-3]+}} = and(q{{[0-3]+}},q{{[0-3]+}})192define void @test21(<16 x i32> %a, <16 x i32> %b) #0 {193entry:194 %0 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a, i32 -1)195 %1 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %b, i32 -1)196 %2 = tail call <64 x i1> @llvm.hexagon.V6.pred.and(<64 x i1> %0, <64 x i1> %1)197 %3 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %2, i32 -1)198 store <16 x i32> %3, ptr @h, align 64199 ret void200}201 202; CHECK-LABEL: test22:203; CHECK: q{{[0-3]+}} = or(q{{[0-3]+}},q{{[0-3]+}})204define void @test22(<16 x i32> %a, <16 x i32> %b) #0 {205entry:206 %0 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a, i32 -1)207 %1 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %b, i32 -1)208 %2 = tail call <64 x i1> @llvm.hexagon.V6.pred.or(<64 x i1> %0, <64 x i1> %1)209 %3 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %2, i32 -1)210 store <16 x i32> %3, ptr @h, align 64211 ret void212}213 214; CHECK-LABEL: test23:215; CHECK: q{{[0-3]+}} = not(q{{[0-3]+}})216define void @test23(<16 x i32> %a) #0 {217entry:218 %0 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a, i32 -1)219 %1 = tail call <64 x i1> @llvm.hexagon.V6.pred.not(<64 x i1> %0)220 %2 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %1, i32 -1)221 store <16 x i32> %2, ptr @h, align 64222 ret void223}224 225; CHECK-LABEL: test24:226; CHECK: q{{[0-3]+}} = xor(q{{[0-3]+}},q{{[0-3]+}})227define void @test24(<16 x i32> %a, <16 x i32> %b) #0 {228entry:229 %0 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a, i32 -1)230 %1 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %b, i32 -1)231 %2 = tail call <64 x i1> @llvm.hexagon.V6.pred.xor(<64 x i1> %0, <64 x i1> %1)232 %3 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %2, i32 -1)233 store <16 x i32> %3, ptr @h, align 64234 ret void235}236 237; CHECK-LABEL: test25:238; CHECK: q{{[0-3]+}} = or(q{{[0-3]+}},!q{{[0-3]+}})239define void @test25(<16 x i32> %a, <16 x i32> %b) #0 {240entry:241 %0 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a, i32 -1)242 %1 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %b, i32 -1)243 %2 = tail call <64 x i1> @llvm.hexagon.V6.pred.or.n(<64 x i1> %0, <64 x i1> %1)244 %3 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %2, i32 -1)245 store <16 x i32> %3, ptr @h, align 64246 ret void247}248 249; CHECK-LABEL: test26:250; CHECK: q{{[0-3]+}} = and(q{{[0-3]+}},!q{{[0-3]+}})251define void @test26(<16 x i32> %a, <16 x i32> %b) #0 {252entry:253 %0 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a, i32 -1)254 %1 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %b, i32 -1)255 %2 = tail call <64 x i1> @llvm.hexagon.V6.pred.and.n(<64 x i1> %0, <64 x i1> %1)256 %3 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %2, i32 -1)257 store <16 x i32> %3, ptr @h, align 64258 ret void259}260 261; CHECK-LABEL: test27:262; CHECK: q{{[0-3]+}} = vcmp.gt(v{{[0-9]+}}.ub,v{{[0-9]+}}.ub)263define void @test27(<16 x i32> %a, <16 x i32> %b) #0 {264entry:265 %0 = tail call <64 x i1> @llvm.hexagon.V6.vgtub(<16 x i32> %a, <16 x i32> %b)266 %1 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %0, i32 -1)267 store <16 x i32> %1, ptr @k, align 64268 ret void269}270 271; CHECK-LABEL: test28:272; CHECK: q{{[0-3]+}} = vcmp.gt(v{{[0-9]+}}.h,v{{[0-9]+}}.h)273define void @test28(<16 x i32> %a, <16 x i32> %b) #0 {274entry:275 %0 = tail call <64 x i1> @llvm.hexagon.V6.vgth(<16 x i32> %a, <16 x i32> %b)276 %1 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %0, i32 -1)277 store <16 x i32> %1, ptr @k, align 64278 ret void279}280 281; CHECK-LABEL: test29:282; CHECK: q{{[0-3]+}} = vcmp.eq(v{{[0-9]+}}.h,v{{[0-9]+}}.h)283define void @test29(<16 x i32> %a, <16 x i32> %b) #0 {284entry:285 %0 = tail call <64 x i1> @llvm.hexagon.V6.veqh(<16 x i32> %a, <16 x i32> %b)286 %1 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %0, i32 -1)287 store <16 x i32> %1, ptr @k, align 64288 ret void289}290 291; CHECK-LABEL: test30:292; CHECK: q{{[0-3]+}} = vcmp.gt(v{{[0-9]+}}.w,v{{[0-9]+}}.w)293define void @test30(<16 x i32> %a, <16 x i32> %b) #0 {294entry:295 %0 = tail call <64 x i1> @llvm.hexagon.V6.vgtw(<16 x i32> %a, <16 x i32> %b)296 %1 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %0, i32 -1)297 store <16 x i32> %1, ptr @k, align 64298 ret void299}300 301; CHECK-LABEL: test31:302; CHECK: q{{[0-3]+}} = vcmp.eq(v{{[0-9]+}}.w,v{{[0-9]+}}.w)303define void @test31(<16 x i32> %a, <16 x i32> %b) #0 {304entry:305 %0 = tail call <64 x i1> @llvm.hexagon.V6.veqw(<16 x i32> %a, <16 x i32> %b)306 %1 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %0, i32 -1)307 store <16 x i32> %1, ptr @k, align 64308 ret void309}310 311; CHECK-LABEL: test32:312; CHECK: q{{[0-3]+}} = vcmp.gt(v{{[0-9]+}}.uh,v{{[0-9]+}}.uh)313define void @test32(<16 x i32> %a, <16 x i32> %b) #0 {314entry:315 %0 = tail call <64 x i1> @llvm.hexagon.V6.vgtuh(<16 x i32> %a, <16 x i32> %b)316 %1 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %0, i32 -1)317 store <16 x i32> %1, ptr @k, align 64318 ret void319}320 321; CHECK-LABEL: test33:322; CHECK: v{{[0-9]+}} |= vand(q{{[0-3]+}},r{{[0-9]+}})323define void @test33(<16 x i32> %a, <16 x i32> %b, i32 %c) #0 {324entry:325 %0 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %b, i32 -1)326 %1 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt.acc(<16 x i32> %a, <64 x i1> %0, i32 %c)327 store <16 x i32> %1, ptr @h, align 64328 ret void329}330 331; CHECK-LABEL: test34:332; CHECK: q{{[0-3]+}} |= vand(v{{[0-9]+}},r{{[0-9]+}})333define void @test34(<16 x i32> %a, <16 x i32> %b, i32 %c) #0 {334entry:335 %0 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a, i32 -1)336 %1 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt.acc(<64 x i1> %0, <16 x i32> %b, i32 %c)337 %2 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %1, i32 -1)338 store <16 x i32> %2, ptr @k, align 64339 ret void340}341 342; CHECK-LABEL: test35:343; CHECK: v{{[0-9]+}} = vand(q{{[0-3]+}},r{{[0-9]+}})344define void @test35(<16 x i32> %a, i32 %b) #0 {345entry:346 %0 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a, i32 -1)347 %1 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %0, i32 %b)348 store <16 x i32> %1, ptr @h, align 64349 ret void350}351 352; CHECK-LABEL: test36:353; CHECK: q{{[0-3]+}} = vand(v{{[0-9]+}},r{{[0-9]+}})354define void @test36(<16 x i32> %a, i32 %b) #0 {355entry:356 %0 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a, i32 %b)357 %1 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %0, i32 -1)358 store <16 x i32> %1, ptr @k, align 64359 ret void360}361 362; CHECK-LABEL: test37:363; CHECK: r{{[0-9]+}}:{{[0-9]+}} = rol(r{{[0-9]+}}:{{[0-9]+}},#38)364define void @test37(i64 %a) #0 {365entry:366 %0 = tail call i64 @llvm.hexagon.S6.rol.i.p(i64 %a, i32 38)367 store i64 %0, ptr @n, align 8368 ret void369}370 371; CHECK-LABEL: test38:372; CHECK: r{{[0-9]+}}:{{[0-9]+}} += rol(r{{[0-9]+}}:{{[0-9]+}},#36)373define void @test38(i64 %a, i64 %b) #0 {374entry:375 %0 = tail call i64 @llvm.hexagon.S6.rol.i.p.acc(i64 %a, i64 %b, i32 36)376 store i64 %0, ptr @n, align 8377 ret void378}379 380; CHECK-LABEL: test39:381; CHECK: r{{[0-9]+}}:{{[0-9]+}} &= rol(r{{[0-9]+}}:{{[0-9]+}},#25)382define void @test39(i64 %a, i64 %b) #0 {383entry:384 %0 = tail call i64 @llvm.hexagon.S6.rol.i.p.and(i64 %a, i64 %b, i32 25)385 store i64 %0, ptr @n, align 8386 ret void387}388 389; CHECK-LABEL: test40:390; CHECK: r{{[0-9]+}}:{{[0-9]+}} -= rol(r{{[0-9]+}}:{{[0-9]+}},#20)391define void @test40(i64 %a, i64 %b) #0 {392entry:393 %0 = tail call i64 @llvm.hexagon.S6.rol.i.p.nac(i64 %a, i64 %b, i32 20)394 store i64 %0, ptr @n, align 8395 ret void396}397 398; CHECK-LABEL: test41:399; CHECK: r{{[0-9]+}}:{{[0-9]+}} |= rol(r{{[0-9]+}}:{{[0-9]+}},#22)400define void @test41(i64 %a, i64 %b) #0 {401entry:402 %0 = tail call i64 @llvm.hexagon.S6.rol.i.p.or(i64 %a, i64 %b, i32 22)403 store i64 %0, ptr @n, align 8404 ret void405}406 407; CHECK-LABEL: test42:408; CHECK: r{{[0-9]+}}:{{[0-9]+}} ^= rol(r{{[0-9]+}}:{{[0-9]+}},#25)409define void @test42(i64 %a, i64 %b) #0 {410entry:411 %0 = tail call i64 @llvm.hexagon.S6.rol.i.p.xacc(i64 %a, i64 %b, i32 25)412 store i64 %0, ptr @n, align 8413 ret void414}415 416; CHECK-LABEL: test43:417; CHECK: r{{[0-9]+}} = rol(r{{[0-9]+}},#14)418define void @test43(i32 %a) #0 {419entry:420 %0 = tail call i32 @llvm.hexagon.S6.rol.i.r(i32 %a, i32 14)421 %conv = sext i32 %0 to i64422 store i64 %conv, ptr @n, align 8423 ret void424}425 426; CHECK-LABEL: test44:427; CHECK: r{{[0-9]+}} += rol(r{{[0-9]+}},#12)428define void @test44(i32 %a, i32 %b) #0 {429entry:430 %0 = tail call i32 @llvm.hexagon.S6.rol.i.r.acc(i32 %a, i32 %b, i32 12)431 store i32 %0, ptr @m, align 4432 ret void433}434 435; CHECK-LABEL: test45:436; CHECK: r{{[0-9]+}} &= rol(r{{[0-9]+}},#18)437define void @test45(i32 %a, i32 %b) #0 {438entry:439 %0 = tail call i32 @llvm.hexagon.S6.rol.i.r.and(i32 %a, i32 %b, i32 18)440 store i32 %0, ptr @m, align 4441 ret void442}443 444; CHECK-LABEL: test46:445; CHECK: r{{[0-9]+}} -= rol(r{{[0-9]+}},#31)446define void @test46(i32 %a, i32 %b) #0 {447entry:448 %0 = tail call i32 @llvm.hexagon.S6.rol.i.r.nac(i32 %a, i32 %b, i32 31)449 store i32 %0, ptr @m, align 4450 ret void451}452 453; CHECK-LABEL: test47:454; CHECK: r{{[0-9]+}} |= rol(r{{[0-9]+}},#30)455define void @test47(i32 %a, i32 %b) #0 {456entry:457 %0 = tail call i32 @llvm.hexagon.S6.rol.i.r.or(i32 %a, i32 %b, i32 30)458 store i32 %0, ptr @m, align 4459 ret void460}461 462; CHECK-LABEL: test48:463; CHECK: r{{[0-9]+}} ^= rol(r{{[0-9]+}},#31)464define void @test48(i32 %a, i32 %b) #0 {465entry:466 %0 = tail call i32 @llvm.hexagon.S6.rol.i.r.xacc(i32 %a, i32 %b, i32 31)467 store i32 %0, ptr @m, align 4468 ret void469}470 471; CHECK-LABEL: test49:472; CHECK: r{{[0-9]+}} = vextract(v{{[0-9]+}},r{{[0-9]+}})473define void @test49(<16 x i32> %a, i32 %b) #0 {474entry:475 %0 = tail call i32 @llvm.hexagon.V6.extractw(<16 x i32> %a, i32 %b)476 store i32 %0, ptr @m, align 4477 ret void478}479 480; CHECK-LABEL: test50:481; CHECK: v{{[0-9]+}} = vsplat(r{{[0-9]+}})482define void @test50(i32 %a) #0 {483entry:484 %0 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 %a)485 store <16 x i32> %0, ptr @k, align 64486 ret void487}488 489; CHECK-LABEL: test51:490; CHECK: q{{[0-3]}} = vsetq(r{{[0-9]+}})491define void @test51(i32 %a) #0 {492entry:493 %0 = tail call <64 x i1> @llvm.hexagon.V6.pred.scalar2(i32 %a)494 %1 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %0, i32 -1)495 store <16 x i32> %1, ptr @k, align 64496 ret void497}498 499; CHECK-LABEL: test52:500; CHECK: v{{[0-9]+}}.b = vlut32(v{{[0-9]+}}.b,v{{[0-9]+}}.b,r{{[0-9]+}})501define void @test52(<16 x i32> %a, <16 x i32> %b, i32 %c) #0 {502entry:503 %0 = tail call <16 x i32> @llvm.hexagon.V6.vlutvvb(<16 x i32> %a, <16 x i32> %b, i32 %c)504 store <16 x i32> %0, ptr @k, align 64505 ret void506}507 508; CHECK-LABEL: test53:509; CHECK: v{{[0-9]+}}.b |= vlut32(v{{[0-9]+}}.b,v{{[0-9]+}}.b,r{{[0-9]+}})510define void @test53(<16 x i32> %a, <16 x i32> %b, <16 x i32> %c, i32 %d) #0 {511entry:512 %0 = tail call <16 x i32> @llvm.hexagon.V6.vlutvvb.oracc(<16 x i32> %a, <16 x i32> %b, <16 x i32> %c, i32 %d)513 store <16 x i32> %0, ptr @k, align 64514 ret void515}516 517; CHECK-LABEL: test54:518; CHECK: v{{[0-9]+}}:{{[0-9]+}}.h |= vlut16(v{{[0-9]+}}.b,v{{[0-9]+}}.h,r{{[0-9]+}})519define void @test54(<32 x i32> %a, <16 x i32> %b, <16 x i32> %c, i32 %d) #0 {520entry:521 %0 = tail call <32 x i32> @llvm.hexagon.V6.vlutvwh.oracc(<32 x i32> %a, <16 x i32> %b, <16 x i32> %c, i32 %d)522 store <32 x i32> %0, ptr @l, align 128523 ret void524}525 526; CHECK-LABEL: test55:527; CHECK: v{{[0-9]+}}:{{[0-9]+}}.h = vlut16(v{{[0-9]+}}.b,v{{[0-9]+}}.h,r{{[0-9]+}})528define void @test55(<16 x i32> %a, <16 x i32> %b, i32 %l) #0 {529entry:530 %0 = tail call <32 x i32> @llvm.hexagon.V6.vlutvwh(<16 x i32> %a, <16 x i32> %b, i32 %l)531 store <32 x i32> %0, ptr @l, align 128532 ret void533}534 535; CHECK-LABEL: test56:536; CHECK: v{{[0-9]+}}.w = vinsert(r{{[0-9]+}})537define void @test56(i32 %b) #0 {538entry:539 %0 = load <16 x i32>, ptr @k, align 64540 %1 = tail call <16 x i32> @llvm.hexagon.V6.vinsertwr(<16 x i32> %0, i32 %b)541 store <16 x i32> %1, ptr @k, align 64542 ret void543}544 545declare <32 x i32> @llvm.hexagon.V6.vrmpybusi(<32 x i32>, i32, i32) #0546declare <32 x i32> @llvm.hexagon.V6.vrsadubi(<32 x i32>, i32, i32) #0547declare <32 x i32> @llvm.hexagon.V6.vrmpyubi(<32 x i32>, i32, i32) #0548declare <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32>, <32 x i32>, i32, i32) #0549declare <32 x i32> @llvm.hexagon.V6.vrsadubi.acc(<32 x i32>, <32 x i32>, i32, i32) #0550declare <32 x i32> @llvm.hexagon.V6.vrmpyubi.acc(<32 x i32>, <32 x i32>, i32, i32) #0551declare <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32>, <16 x i32>, i32) #0552declare <16 x i32> @llvm.hexagon.V6.vlalignb(<16 x i32>, <16 x i32>, i32) #0553declare <16 x i32> @llvm.hexagon.V6.vasrwh(<16 x i32>, <16 x i32>, i32) #0554declare <16 x i32> @llvm.hexagon.V6.vasrwhsat(<16 x i32>, <16 x i32>, i32) #0555declare <16 x i32> @llvm.hexagon.V6.vasrwhrndsat(<16 x i32>, <16 x i32>, i32) #0556declare <16 x i32> @llvm.hexagon.V6.vasrwuhsat(<16 x i32>, <16 x i32>, i32) #0557declare <16 x i32> @llvm.hexagon.V6.vasrhubsat(<16 x i32>, <16 x i32>, i32) #0558declare <16 x i32> @llvm.hexagon.V6.vasrhubrndsat(<16 x i32>, <16 x i32>, i32) #0559declare <16 x i32> @llvm.hexagon.V6.vasrhbrndsat(<16 x i32>, <16 x i32>, i32) #0560declare <32 x i32> @llvm.hexagon.V6.vunpackob(<32 x i32>, <16 x i32>) #0561declare <32 x i32> @llvm.hexagon.V6.vunpackoh(<32 x i32>, <16 x i32>) #0562declare <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32>, <16 x i32>, i32) #0563declare <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32>, <16 x i32>, i32) #0564declare <16 x i32> @llvm.hexagon.V6.vmux(<64 x i1>, <16 x i32>, <16 x i32>) #0565declare <64 x i1> @llvm.hexagon.V6.pred.and(<64 x i1>, <64 x i1>) #0566declare <64 x i1> @llvm.hexagon.V6.pred.or(<64 x i1>, <64 x i1>) #0567declare <64 x i1> @llvm.hexagon.V6.pred.not(<64 x i1>) #0568declare <64 x i1> @llvm.hexagon.V6.pred.xor(<64 x i1>, <64 x i1>) #0569declare <64 x i1> @llvm.hexagon.V6.pred.or.n(<64 x i1>, <64 x i1>) #0570declare <64 x i1> @llvm.hexagon.V6.pred.and.n(<64 x i1>, <64 x i1>) #0571declare <64 x i1> @llvm.hexagon.V6.vgtub(<16 x i32>, <16 x i32>) #0572declare <64 x i1> @llvm.hexagon.V6.vgth(<16 x i32>, <16 x i32>) #0573declare <64 x i1> @llvm.hexagon.V6.veqh(<16 x i32>, <16 x i32>) #0574declare <64 x i1> @llvm.hexagon.V6.vgtw(<16 x i32>, <16 x i32>) #0575declare <64 x i1> @llvm.hexagon.V6.veqw(<16 x i32>, <16 x i32>) #0576declare <64 x i1> @llvm.hexagon.V6.vgtuh(<16 x i32>, <16 x i32>) #0577declare <16 x i32> @llvm.hexagon.V6.vandqrt.acc(<16 x i32>, <64 x i1>, i32) #0578declare <64 x i1> @llvm.hexagon.V6.vandvrt.acc(<64 x i1>, <16 x i32>, i32) #0579declare <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1>, i32) #0580declare <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32>, i32) #0581declare i64 @llvm.hexagon.S6.rol.i.p(i64, i32) #0582declare i64 @llvm.hexagon.S6.rol.i.p.acc(i64, i64, i32) #0583declare i64 @llvm.hexagon.S6.rol.i.p.and(i64, i64, i32) #0584declare i64 @llvm.hexagon.S6.rol.i.p.nac(i64, i64, i32) #0585declare i64 @llvm.hexagon.S6.rol.i.p.or(i64, i64, i32) #0586declare i64 @llvm.hexagon.S6.rol.i.p.xacc(i64, i64, i32) #0587declare i32 @llvm.hexagon.S6.rol.i.r(i32, i32) #0588declare i32 @llvm.hexagon.S6.rol.i.r.acc(i32, i32, i32) #0589declare i32 @llvm.hexagon.S6.rol.i.r.and(i32, i32, i32) #0590declare i32 @llvm.hexagon.S6.rol.i.r.nac(i32, i32, i32) #0591declare i32 @llvm.hexagon.S6.rol.i.r.or(i32, i32, i32) #0592declare i32 @llvm.hexagon.S6.rol.i.r.xacc(i32, i32, i32) #0593declare i32 @llvm.hexagon.V6.extractw(<16 x i32>, i32) #0594declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #0595declare <64 x i1> @llvm.hexagon.V6.pred.scalar2(i32) #0596declare <16 x i32> @llvm.hexagon.V6.vlutvvb(<16 x i32>, <16 x i32>, i32) #0597declare <32 x i32> @llvm.hexagon.V6.vlutvwh(<16 x i32>, <16 x i32>, i32) #0598declare <16 x i32> @llvm.hexagon.V6.vlutvvb.oracc(<16 x i32>, <16 x i32>, <16 x i32>, i32) #0599declare <32 x i32> @llvm.hexagon.V6.vlutvwh.oracc(<32 x i32>, <16 x i32>, <16 x i32>, i32) #0600declare <16 x i32> @llvm.hexagon.V6.vinsertwr(<16 x i32>, i32) #0601 602attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }603