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1; RUN: llc -mtriple=hexagon < %s | FileCheck %s2 3@d = external global <16 x i32>4@c = external global <32 x i32>5 6; CHECK-LABEL: test1:7; CHECK: v{{[0-9]+}}.b = vpacke(v{{[0-9]+}}.h,v{{[0-9]+}}.h)8define void @test1(<16 x i32> %a, <16 x i32> %b) #0 {9entry:10 %0 = tail call <16 x i32> @llvm.hexagon.V6.vpackeb(<16 x i32> %a, <16 x i32> %b)11 store <16 x i32> %0, ptr @d, align 6412 ret void13}14 15; CHECK-LABEL: test2:16; CHECK: v{{[0-9]+}}.h = vpacke(v{{[0-9]+}}.w,v{{[0-9]+}}.w)17define void @test2(<16 x i32> %a, <16 x i32> %b) #0 {18entry:19 %0 = tail call <16 x i32> @llvm.hexagon.V6.vpackeh(<16 x i32> %a, <16 x i32> %b)20 store <16 x i32> %0, ptr @d, align 6421 ret void22}23 24; CHECK-LABEL: test3:25; CHECK: v{{[0-9]+}}.ub = vpack(v{{[0-9]+}}.h,v{{[0-9]+}}.h):sat26define void @test3(<16 x i32> %a, <16 x i32> %b) #0 {27entry:28 %0 = tail call <16 x i32> @llvm.hexagon.V6.vpackhub.sat(<16 x i32> %a, <16 x i32> %b)29 store <16 x i32> %0, ptr @d, align 6430 ret void31}32 33; CHECK-LABEL: test4:34; CHECK: v{{[0-9]+}}.b = vpack(v{{[0-9]+}}.h,v{{[0-9]+}}.h):sat35define void @test4(<16 x i32> %a, <16 x i32> %b) #0 {36entry:37 %0 = tail call <16 x i32> @llvm.hexagon.V6.vpackhb.sat(<16 x i32> %a, <16 x i32> %b)38 store <16 x i32> %0, ptr @d, align 6439 ret void40}41 42; CHECK-LABEL: test5:43; CHECK: v{{[0-9]+}}.uh = vpack(v{{[0-9]+}}.w,v{{[0-9]+}}.w):sat44define void @test5(<16 x i32> %a, <16 x i32> %b) #0 {45entry:46 %0 = tail call <16 x i32> @llvm.hexagon.V6.vpackwuh.sat(<16 x i32> %a, <16 x i32> %b)47 store <16 x i32> %0, ptr @d, align 6448 ret void49}50 51; CHECK-LABEL: test6:52; CHECK: v{{[0-9]+}}.h = vpack(v{{[0-9]+}}.w,v{{[0-9]+}}.w):sat53define void @test6(<16 x i32> %a, <16 x i32> %b) #0 {54entry:55 %0 = tail call <16 x i32> @llvm.hexagon.V6.vpackwh.sat(<16 x i32> %a, <16 x i32> %b)56 store <16 x i32> %0, ptr @d, align 6457 ret void58}59 60; CHECK-LABEL: test7:61; CHECK: v{{[0-9]+}}.b = vpacko(v{{[0-9]+}}.h,v{{[0-9]+}}.h)62define void @test7(<16 x i32> %a, <16 x i32> %b) #0 {63entry:64 %0 = tail call <16 x i32> @llvm.hexagon.V6.vpackob(<16 x i32> %a, <16 x i32> %b)65 store <16 x i32> %0, ptr @d, align 6466 ret void67}68 69; CHECK-LABEL: test8:70; CHECK: v{{[0-9]+}}.h = vpacko(v{{[0-9]+}}.w,v{{[0-9]+}}.w)71define void @test8(<16 x i32> %a, <16 x i32> %b) #0 {72entry:73 %0 = tail call <16 x i32> @llvm.hexagon.V6.vpackoh(<16 x i32> %a, <16 x i32> %b)74 store <16 x i32> %0, ptr @d, align 6475 ret void76}77 78; CHECK-LABEL: test9:79; CHECK: v{{[0-9]+}}:{{[0-9]+}}.uh = vunpack(v{{[0-9]+}}.ub)80define void @test9(<16 x i32> %a) #0 {81entry:82 %0 = tail call <32 x i32> @llvm.hexagon.V6.vunpackub(<16 x i32> %a)83 store <32 x i32> %0, ptr @c, align 12884 ret void85}86 87; CHECK-LABEL: test10:88; CHECK: v{{[0-9]+}}:{{[0-9]+}}.uw = vunpack(v{{[0-9]+}}.uh)89define void @test10(<16 x i32> %a) #0 {90entry:91 %0 = tail call <32 x i32> @llvm.hexagon.V6.vunpackuh(<16 x i32> %a)92 store <32 x i32> %0, ptr @c, align 12893 ret void94}95 96; CHECK-LABEL: test11:97; CHECK: v{{[0-9]+}}:{{[0-9]+}}.h = vunpack(v{{[0-9]+}}.b)98define void @test11(<16 x i32> %a) #0 {99entry:100 %0 = tail call <32 x i32> @llvm.hexagon.V6.vunpackb(<16 x i32> %a)101 store <32 x i32> %0, ptr @c, align 128102 ret void103}104 105; CHECK-LABEL: test12:106; CHECK: v{{[0-9]+}}:{{[0-9]+}}.w = vunpack(v{{[0-9]+}}.h)107define void @test12(<16 x i32> %a) #0 {108entry:109 %0 = tail call <32 x i32> @llvm.hexagon.V6.vunpackh(<16 x i32> %a)110 store <32 x i32> %0, ptr @c, align 128111 ret void112}113 114; CHECK-LABEL: test13:115; CHECK: v{{[0-9]+}}.h = vdeal(v{{[0-9]+}}.h)116define void @test13(<16 x i32> %a) #0 {117entry:118 %0 = tail call <16 x i32> @llvm.hexagon.V6.vdealh(<16 x i32> %a)119 store <16 x i32> %0, ptr @d, align 64120 ret void121}122 123; CHECK-LABEL: test14:124; CHECK: v{{[0-9]+}}.b = vdeal(v{{[0-9]+}}.b)125define void @test14(<16 x i32> %a) #0 {126entry:127 %0 = tail call <16 x i32> @llvm.hexagon.V6.vdealb(<16 x i32> %a)128 store <16 x i32> %0, ptr @d, align 64129 ret void130}131 132; CHECK-LABEL: test15:133; CHECK: v{{[0-9]+}}.h = vshuff(v{{[0-9]+}}.h)134define void @test15(<16 x i32> %a) #0 {135entry:136 %0 = tail call <16 x i32> @llvm.hexagon.V6.vshuffh(<16 x i32> %a)137 store <16 x i32> %0, ptr @d, align 64138 ret void139}140 141; CHECK-LABEL: test16:142; CHECK: v{{[0-9]+}}.b = vshuff(v{{[0-9]+}}.b)143define void @test16(<16 x i32> %a) #0 {144entry:145 %0 = tail call <16 x i32> @llvm.hexagon.V6.vshuffb(<16 x i32> %a)146 store <16 x i32> %0, ptr @d, align 64147 ret void148}149 150declare <16 x i32> @llvm.hexagon.V6.vpackeb(<16 x i32>, <16 x i32>) #0151declare <16 x i32> @llvm.hexagon.V6.vpackeh(<16 x i32>, <16 x i32>) #0152declare <16 x i32> @llvm.hexagon.V6.vpackhub.sat(<16 x i32>, <16 x i32>) #0153declare <16 x i32> @llvm.hexagon.V6.vpackhb.sat(<16 x i32>, <16 x i32>) #0154declare <16 x i32> @llvm.hexagon.V6.vpackwuh.sat(<16 x i32>, <16 x i32>) #0155declare <16 x i32> @llvm.hexagon.V6.vpackwh.sat(<16 x i32>, <16 x i32>) #0156declare <16 x i32> @llvm.hexagon.V6.vpackob(<16 x i32>, <16 x i32>) #0157declare <16 x i32> @llvm.hexagon.V6.vpackoh(<16 x i32>, <16 x i32>) #0158declare <32 x i32> @llvm.hexagon.V6.vunpackub(<16 x i32>) #0159declare <32 x i32> @llvm.hexagon.V6.vunpackuh(<16 x i32>) #0160declare <32 x i32> @llvm.hexagon.V6.vunpackb(<16 x i32>) #0161declare <32 x i32> @llvm.hexagon.V6.vunpackh(<16 x i32>) #0162declare <16 x i32> @llvm.hexagon.V6.vdealh(<16 x i32>) #0163declare <16 x i32> @llvm.hexagon.V6.vdealb(<16 x i32>) #0164declare <16 x i32> @llvm.hexagon.V6.vshuffh(<16 x i32>) #0165declare <16 x i32> @llvm.hexagon.V6.vshuffb(<16 x i32>) #0166 167attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }168