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1; RUN: llc -mtriple=hexagon < %s | FileCheck %s2 3@c = external global <64 x i32>4@d = external global <32 x i32>5 6; CHECK-LABEL: test1:7; CHECK: v{{[0-9]+}}:{{[0-9]+}}.h += vtmpy(v{{[0-9]+}}:{{[0-9]+}}.b,r{{[0-9]+}}.b)8define void @test1(<64 x i32> %a, i32 %b) #0 {9entry:10 %a.addr = alloca <64 x i32>, align 25611 %b.addr = alloca i32, align 412 store <64 x i32> %a, ptr %a.addr, align 25613 store i32 %b, ptr %b.addr, align 414 %0 = load <64 x i32>, ptr @c, align 25615 %1 = load <64 x i32>, ptr %a.addr, align 25616 %2 = load i32, ptr %b.addr, align 417 %3 = call <64 x i32> @llvm.hexagon.V6.vtmpyb.acc.128B(<64 x i32> %0, <64 x i32> %1, i32 %2)18 store <64 x i32> %3, ptr @c, align 25619 ret void20}21 22; CHECK-LABEL: test2:23; CHECK: v{{[0-9]+}}:{{[0-9]+}}.h += vtmpy(v{{[0-9]+}}:{{[0-9]+}}.ub,r{{[0-9]+}}.b)24define void @test2(<64 x i32> %a, i32 %b) #0 {25entry:26 %a.addr = alloca <64 x i32>, align 25627 %b.addr = alloca i32, align 428 store <64 x i32> %a, ptr %a.addr, align 25629 store i32 %b, ptr %b.addr, align 430 %0 = load <64 x i32>, ptr @c, align 25631 %1 = load <64 x i32>, ptr %a.addr, align 25632 %2 = load i32, ptr %b.addr, align 433 %3 = call <64 x i32> @llvm.hexagon.V6.vtmpybus.acc.128B(<64 x i32> %0, <64 x i32> %1, i32 %2)34 store <64 x i32> %3, ptr @c, align 25635 ret void36}37 38; CHECK-LABEL: test3:39; CHECK: v{{[0-9]+}}:{{[0-9]+}}.w += vtmpy(v{{[0-9]+}}:{{[0-9]+}}.h,r{{[0-9]+}}.b)40define void @test3(<64 x i32> %a, i32 %b) #0 {41entry:42 %a.addr = alloca <64 x i32>, align 25643 %b.addr = alloca i32, align 444 store <64 x i32> %a, ptr %a.addr, align 25645 store i32 %b, ptr %b.addr, align 446 %0 = load <64 x i32>, ptr @c, align 25647 %1 = load <64 x i32>, ptr %a.addr, align 25648 %2 = load i32, ptr %b.addr, align 449 %3 = call <64 x i32> @llvm.hexagon.V6.vtmpyhb.acc.128B(<64 x i32> %0, <64 x i32> %1, i32 %2)50 store <64 x i32> %3, ptr @c, align 25651 ret void52}53 54; CHECK-LABEL: test4:55; CHECK: v{{[0-9]+}}.w += vdmpy(v{{[0-9]+}}.h,r{{[0-9]+}}.b)56define void @test4(<32 x i32> %a, i32 %b) #0 {57entry:58 %a.addr = alloca <32 x i32>, align 12859 %b.addr = alloca i32, align 460 store <32 x i32> %a, ptr %a.addr, align 12861 store i32 %b, ptr %b.addr, align 462 %0 = load <32 x i32>, ptr @d, align 12863 %1 = load <32 x i32>, ptr %a.addr, align 12864 %2 = load i32, ptr %b.addr, align 465 %3 = call <32 x i32> @llvm.hexagon.V6.vdmpyhb.acc.128B(<32 x i32> %0, <32 x i32> %1, i32 %2)66 store <32 x i32> %3, ptr @d, align 12867 ret void68}69 70; CHECK-LABEL: test5:71; CHECK: v{{[0-9]+}}.uw += vrmpy(v{{[0-9]+}}.ub,r{{[0-9]+}}.ub)72define void @test5(<32 x i32> %a, i32 %b) #0 {73entry:74 %a.addr = alloca <32 x i32>, align 12875 %b.addr = alloca i32, align 476 store <32 x i32> %a, ptr %a.addr, align 12877 store i32 %b, ptr %b.addr, align 478 %0 = load <32 x i32>, ptr @d, align 12879 %1 = load <32 x i32>, ptr %a.addr, align 12880 %2 = load i32, ptr %b.addr, align 481 %3 = call <32 x i32> @llvm.hexagon.V6.vrmpyub.acc.128B(<32 x i32> %0, <32 x i32> %1, i32 %2)82 store <32 x i32> %3, ptr @d, align 12883 ret void84}85 86; CHECK-LABEL: test6:87; CHECK: v{{[0-9]+}}.w += vrmpy(v{{[0-9]+}}.ub,r{{[0-9]+}}.b)88define void @test6(<32 x i32> %a, i32 %b) #0 {89entry:90 %a.addr = alloca <32 x i32>, align 12891 %b.addr = alloca i32, align 492 store <32 x i32> %a, ptr %a.addr, align 12893 store i32 %b, ptr %b.addr, align 494 %0 = load <32 x i32>, ptr @d, align 12895 %1 = load <32 x i32>, ptr %a.addr, align 12896 %2 = load i32, ptr %b.addr, align 497 %3 = call <32 x i32> @llvm.hexagon.V6.vrmpybus.acc.128B(<32 x i32> %0, <32 x i32> %1, i32 %2)98 store <32 x i32> %3, ptr @d, align 12899 ret void100}101 102; CHECK-LABEL: test7:103; CHECK: v{{[0-9]+}}.h += vdmpy(v{{[0-9]+}}.ub,r{{[0-9]+}}.b)104define void @test7(<32 x i32> %a, i32 %b) #0 {105entry:106 %a.addr = alloca <32 x i32>, align 128107 %b.addr = alloca i32, align 4108 store <32 x i32> %a, ptr %a.addr, align 128109 store i32 %b, ptr %b.addr, align 4110 %0 = load <32 x i32>, ptr @d, align 128111 %1 = load <32 x i32>, ptr %a.addr, align 128112 %2 = load i32, ptr %b.addr, align 4113 %3 = call <32 x i32> @llvm.hexagon.V6.vdmpybus.acc.128B(<32 x i32> %0, <32 x i32> %1, i32 %2)114 store <32 x i32> %3, ptr @d, align 128115 ret void116}117 118; CHECK-LABEL: test8:119; CHECK: v{{[0-9]+}}:{{[0-9]+}}.h += vdmpy(v{{[0-9]+}}:{{[0-9]+}}.ub,r{{[0-9]+}}.b)120define void @test8(<64 x i32> %a, i32 %b) #0 {121entry:122 %a.addr = alloca <64 x i32>, align 256123 %b.addr = alloca i32, align 4124 store <64 x i32> %a, ptr %a.addr, align 256125 store i32 %b, ptr %b.addr, align 4126 %0 = load <64 x i32>, ptr @c, align 256127 %1 = load <64 x i32>, ptr %a.addr, align 256128 %2 = load i32, ptr %b.addr, align 4129 %3 = call <64 x i32> @llvm.hexagon.V6.vdmpybus.dv.acc.128B(<64 x i32> %0, <64 x i32> %1, i32 %2)130 store <64 x i32> %3, ptr @c, align 256131 ret void132}133 134; CHECK-LABEL: test9:135; CHECK: v{{[0-9]+}}.w += vdmpy(v{{[0-9]+}}.h,r{{[0-9]+}}.uh):sat136define void @test9(<32 x i32> %a, i32 %b) #0 {137entry:138 %a.addr = alloca <32 x i32>, align 128139 %b.addr = alloca i32, align 4140 store <32 x i32> %a, ptr %a.addr, align 128141 store i32 %b, ptr %b.addr, align 4142 %0 = load <32 x i32>, ptr @d, align 128143 %1 = load <32 x i32>, ptr %a.addr, align 128144 %2 = load i32, ptr %b.addr, align 4145 %3 = call <32 x i32> @llvm.hexagon.V6.vdmpyhsusat.acc.128B(<32 x i32> %0, <32 x i32> %1, i32 %2)146 store <32 x i32> %3, ptr @d, align 128147 ret void148}149 150; CHECK-LABEL: test10:151; CHECK: v{{[0-9]+}}.w += vdmpy(v{{[0-9]+}}:{{[0-9]+}}.h,r{{[0-9]+}}.uh,#1):sat152define void @test10(<64 x i32> %a, i32 %b) #0 {153entry:154 %a.addr = alloca <64 x i32>, align 256155 %b.addr = alloca i32, align 4156 store <64 x i32> %a, ptr %a.addr, align 256157 store i32 %b, ptr %b.addr, align 4158 %0 = load <32 x i32>, ptr @d, align 128159 %1 = load <64 x i32>, ptr %a.addr, align 256160 %2 = load i32, ptr %b.addr, align 4161 %3 = call <32 x i32> @llvm.hexagon.V6.vdmpyhsuisat.acc.128B(<32 x i32> %0, <64 x i32> %1, i32 %2)162 store <32 x i32> %3, ptr @d, align 128163 ret void164}165 166; CHECK-LABEL: test11:167; CHECK: v{{[0-9]+}}.w += vdmpy(v{{[0-9]+}}:{{[0-9]+}}.h,r{{[0-9]+}}.h):sat168define void @test11(<64 x i32> %a, i32 %b) #0 {169entry:170 %a.addr = alloca <64 x i32>, align 256171 %b.addr = alloca i32, align 4172 store <64 x i32> %a, ptr %a.addr, align 256173 store i32 %b, ptr %b.addr, align 4174 %0 = load <32 x i32>, ptr @d, align 128175 %1 = load <64 x i32>, ptr %a.addr, align 256176 %2 = load i32, ptr %b.addr, align 4177 %3 = call <32 x i32> @llvm.hexagon.V6.vdmpyhisat.acc.128B(<32 x i32> %0, <64 x i32> %1, i32 %2)178 store <32 x i32> %3, ptr @d, align 128179 ret void180}181 182; CHECK-LABEL: test12:183; CHECK: v{{[0-9]+}}.w += vdmpy(v{{[0-9]+}}.h,r{{[0-9]+}}.h):sat184define void @test12(<32 x i32> %a, i32 %b) #0 {185entry:186 %a.addr = alloca <32 x i32>, align 128187 %b.addr = alloca i32, align 4188 store <32 x i32> %a, ptr %a.addr, align 128189 store i32 %b, ptr %b.addr, align 4190 %0 = load <32 x i32>, ptr @d, align 128191 %1 = load <32 x i32>, ptr %a.addr, align 128192 %2 = load i32, ptr %b.addr, align 4193 %3 = call <32 x i32> @llvm.hexagon.V6.vdmpyhsat.acc.128B(<32 x i32> %0, <32 x i32> %1, i32 %2)194 store <32 x i32> %3, ptr @d, align 128195 ret void196}197 198; CHECK-LABEL: test13:199; CHECK: v{{[0-9]+}}:{{[0-9]+}}.w += vdmpy(v{{[0-9]+}}:{{[0-9]+}}.h,r{{[0-9]+}}.b)200define void @test13(<64 x i32> %a, i32 %b) #0 {201entry:202 %a.addr = alloca <64 x i32>, align 256203 %b.addr = alloca i32, align 4204 store <64 x i32> %a, ptr %a.addr, align 256205 store i32 %b, ptr %b.addr, align 4206 %0 = load <64 x i32>, ptr @c, align 256207 %1 = load <64 x i32>, ptr %a.addr, align 256208 %2 = load i32, ptr %b.addr, align 4209 %3 = call <64 x i32> @llvm.hexagon.V6.vdmpyhb.dv.acc.128B(<64 x i32> %0, <64 x i32> %1, i32 %2)210 store <64 x i32> %3, ptr @c, align 256211 ret void212}213 214; CHECK-LABEL: test14:215; CHECK: v{{[0-9]+}}:{{[0-9]+}}.h += vmpy(v{{[0-9]+}}.ub,r{{[0-9]+}}.b)216define void @test14(<32 x i32> %a, i32 %b) #0 {217entry:218 %a.addr = alloca <32 x i32>, align 128219 %b.addr = alloca i32, align 4220 store <32 x i32> %a, ptr %a.addr, align 128221 store i32 %b, ptr %b.addr, align 4222 %0 = load <64 x i32>, ptr @c, align 256223 %1 = load <32 x i32>, ptr %a.addr, align 128224 %2 = load i32, ptr %b.addr, align 4225 %3 = call <64 x i32> @llvm.hexagon.V6.vmpybus.acc.128B(<64 x i32> %0, <32 x i32> %1, i32 %2)226 store <64 x i32> %3, ptr @c, align 256227 ret void228}229 230; CHECK-LABEL: test15:231; CHECK: v{{[0-9]+}}:{{[0-9]+}}.h += vmpa(v{{[0-9]+}}:{{[0-9]+}}.ub,r{{[0-9]+}}.b)232define void @test15(<64 x i32> %a, i32 %b) #0 {233entry:234 %a.addr = alloca <64 x i32>, align 256235 %b.addr = alloca i32, align 4236 store <64 x i32> %a, ptr %a.addr, align 256237 store i32 %b, ptr %b.addr, align 4238 %0 = load <64 x i32>, ptr @c, align 256239 %1 = load <64 x i32>, ptr %a.addr, align 256240 %2 = load i32, ptr %b.addr, align 4241 %3 = call <64 x i32> @llvm.hexagon.V6.vmpabus.acc.128B(<64 x i32> %0, <64 x i32> %1, i32 %2)242 store <64 x i32> %3, ptr @c, align 256243 ret void244}245 246; CHECK-LABEL: test16:247; CHECK: v{{[0-9]+}}:{{[0-9]+}}.w += vmpa(v{{[0-9]+}}:{{[0-9]+}}.h,r{{[0-9]+}}.b)248define void @test16(<64 x i32> %a, i32 %b) #0 {249entry:250 %a.addr = alloca <64 x i32>, align 256251 %b.addr = alloca i32, align 4252 store <64 x i32> %a, ptr %a.addr, align 256253 store i32 %b, ptr %b.addr, align 4254 %0 = load <64 x i32>, ptr @c, align 256255 %1 = load <64 x i32>, ptr %a.addr, align 256256 %2 = load i32, ptr %b.addr, align 4257 %3 = call <64 x i32> @llvm.hexagon.V6.vmpahb.acc.128B(<64 x i32> %0, <64 x i32> %1, i32 %2)258 store <64 x i32> %3, ptr @c, align 256259 ret void260}261 262; CHECK-LABEL: test17:263; CHECK: v{{[0-9]+}}:{{[0-9]+}}.w += vmpy(v{{[0-9]+}}.h,r{{[0-9]+}}.h):sat264define void @test17(<32 x i32> %a, i32 %b) #0 {265entry:266 %a.addr = alloca <32 x i32>, align 128267 %b.addr = alloca i32, align 4268 store <32 x i32> %a, ptr %a.addr, align 128269 store i32 %b, ptr %b.addr, align 4270 %0 = load <64 x i32>, ptr @c, align 256271 %1 = load <32 x i32>, ptr %a.addr, align 128272 %2 = load i32, ptr %b.addr, align 4273 %3 = call <64 x i32> @llvm.hexagon.V6.vmpyhsat.acc.128B(<64 x i32> %0, <32 x i32> %1, i32 %2)274 store <64 x i32> %3, ptr @c, align 256275 ret void276}277 278; CHECK-LABEL: test18:279; CHECK: v{{[0-9]+}}:{{[0-9]+}}.uw += vmpy(v{{[0-9]+}}.uh,r{{[0-9]+}}.uh)280define void @test18(<32 x i32> %a, i32 %b) #0 {281entry:282 %a.addr = alloca <32 x i32>, align 128283 %b.addr = alloca i32, align 4284 store <32 x i32> %a, ptr %a.addr, align 128285 store i32 %b, ptr %b.addr, align 4286 %0 = load <64 x i32>, ptr @c, align 256287 %1 = load <32 x i32>, ptr %a.addr, align 128288 %2 = load i32, ptr %b.addr, align 4289 %3 = call <64 x i32> @llvm.hexagon.V6.vmpyuh.acc.128B(<64 x i32> %0, <32 x i32> %1, i32 %2)290 store <64 x i32> %3, ptr @c, align 256291 ret void292}293 294; CHECK-LABEL: test19:295; CHECK: v{{[0-9]+}}.w += vmpyi(v{{[0-9]+}}.w,r{{[0-9]+}}.b)296define void @test19(<32 x i32> %a, i32 %b) #0 {297entry:298 %a.addr = alloca <32 x i32>, align 128299 %b.addr = alloca i32, align 4300 store <32 x i32> %a, ptr %a.addr, align 128301 store i32 %b, ptr %b.addr, align 4302 %0 = load <32 x i32>, ptr @d, align 128303 %1 = load <32 x i32>, ptr %a.addr, align 128304 %2 = load i32, ptr %b.addr, align 4305 %3 = call <32 x i32> @llvm.hexagon.V6.vmpyiwb.acc.128B(<32 x i32> %0, <32 x i32> %1, i32 %2)306 store <32 x i32> %3, ptr @d, align 128307 ret void308}309 310; CHECK-LABEL: test20:311; CHECK: v{{[0-9]+}}.w += vmpyi(v{{[0-9]+}}.w,r{{[0-9]+}}.h)312define void @test20(<32 x i32> %a, i32 %b) #0 {313entry:314 %a.addr = alloca <32 x i32>, align 128315 %b.addr = alloca i32, align 4316 store <32 x i32> %a, ptr %a.addr, align 128317 store i32 %b, ptr %b.addr, align 4318 %0 = load <32 x i32>, ptr @d, align 128319 %1 = load <32 x i32>, ptr %a.addr, align 128320 %2 = load i32, ptr %b.addr, align 4321 %3 = call <32 x i32> @llvm.hexagon.V6.vmpyiwh.acc.128B(<32 x i32> %0, <32 x i32> %1, i32 %2)322 store <32 x i32> %3, ptr @d, align 128323 ret void324}325 326; CHECK-LABEL: test21:327; CHECK: v{{[0-9]+}}:{{[0-9]+}}.uw += vdsad(v{{[0-9]+}}:{{[0-9]+}}.uh,r{{[0-9]+}}.uh)328define void @test21(<64 x i32> %a, i32 %b) #0 {329entry:330 %a.addr = alloca <64 x i32>, align 256331 %b.addr = alloca i32, align 4332 store <64 x i32> %a, ptr %a.addr, align 256333 store i32 %b, ptr %b.addr, align 4334 %0 = load <64 x i32>, ptr @c, align 256335 %1 = load <64 x i32>, ptr %a.addr, align 256336 %2 = load i32, ptr %b.addr, align 4337 %3 = call <64 x i32> @llvm.hexagon.V6.vdsaduh.acc.128B(<64 x i32> %0, <64 x i32> %1, i32 %2)338 store <64 x i32> %3, ptr @c, align 256339 ret void340}341 342; CHECK-LABEL: test22:343; CHECK: v{{[0-9]+}}.h += vmpyi(v{{[0-9]+}}.h,r{{[0-9]+}}.b)344define void @test22(<32 x i32> %a, i32 %b) #0 {345entry:346 %a.addr = alloca <32 x i32>, align 128347 %b.addr = alloca i32, align 4348 store <32 x i32> %a, ptr %a.addr, align 128349 store i32 %b, ptr %b.addr, align 4350 %0 = load <32 x i32>, ptr @d, align 128351 %1 = load <32 x i32>, ptr %a.addr, align 128352 %2 = load i32, ptr %b.addr, align 4353 %3 = call <32 x i32> @llvm.hexagon.V6.vmpyihb.acc.128B(<32 x i32> %0, <32 x i32> %1, i32 %2)354 store <32 x i32> %3, ptr @d, align 128355 ret void356}357 358; CHECK-LABEL: test23:359; CHECK: v{{[0-9]+}}.w += vasl(v{{[0-9]+}}.w,r{{[0-9]+}})360define void @test23(<32 x i32> %a, i32 %b) #0 {361entry:362 %a.addr = alloca <32 x i32>, align 128363 %b.addr = alloca i32, align 4364 store <32 x i32> %a, ptr %a.addr, align 128365 store i32 %b, ptr %b.addr, align 4366 %0 = load <32 x i32>, ptr @d, align 128367 %1 = load <32 x i32>, ptr %a.addr, align 128368 %2 = load i32, ptr %b.addr, align 4369 %3 = call <32 x i32> @llvm.hexagon.V6.vaslw.acc.128B(<32 x i32> %0, <32 x i32> %1, i32 %2)370 store <32 x i32> %3, ptr @d, align 128371 ret void372}373 374; CHECK-LABEL: test24:375; CHECK: v{{[0-9]+}}.w += vasr(v{{[0-9]+}}.w,r{{[0-9]+}})376define void @test24(<32 x i32> %a, i32 %b) #0 {377entry:378 %a.addr = alloca <32 x i32>, align 128379 %b.addr = alloca i32, align 4380 store <32 x i32> %a, ptr %a.addr, align 128381 store i32 %b, ptr %b.addr, align 4382 %0 = load <32 x i32>, ptr @d, align 128383 %1 = load <32 x i32>, ptr %a.addr, align 128384 %2 = load i32, ptr %b.addr, align 4385 %3 = call <32 x i32> @llvm.hexagon.V6.vasrw.acc.128B(<32 x i32> %0, <32 x i32> %1, i32 %2)386 store <32 x i32> %3, ptr @d, align 128387 ret void388}389 390; CHECK-LABEL: test25:391; CHECK: v{{[0-9]+}}:{{[0-9]+}}.uh += vmpy(v{{[0-9]+}}.ub,r{{[0-9]+}}.ub)392define void @test25(<32 x i32> %a, i32 %b) #0 {393entry:394 %a.addr = alloca <32 x i32>, align 128395 %b.addr = alloca i32, align 4396 store <32 x i32> %a, ptr %a.addr, align 128397 store i32 %b, ptr %b.addr, align 4398 %0 = load <64 x i32>, ptr @c, align 256399 %1 = load <32 x i32>, ptr %a.addr, align 128400 %2 = load i32, ptr %b.addr, align 4401 %3 = call <64 x i32> @llvm.hexagon.V6.vmpyub.acc.128B(<64 x i32> %0, <32 x i32> %1, i32 %2)402 store <64 x i32> %3, ptr @c, align 256403 ret void404}405 406declare <64 x i32> @llvm.hexagon.V6.vtmpyb.acc.128B(<64 x i32>, <64 x i32>, i32) #0407declare <64 x i32> @llvm.hexagon.V6.vtmpybus.acc.128B(<64 x i32>, <64 x i32>, i32) #0408declare <64 x i32> @llvm.hexagon.V6.vtmpyhb.acc.128B(<64 x i32>, <64 x i32>, i32) #0409declare <32 x i32> @llvm.hexagon.V6.vdmpyhb.acc.128B(<32 x i32>, <32 x i32>, i32) #0410declare <32 x i32> @llvm.hexagon.V6.vrmpyub.acc.128B(<32 x i32>, <32 x i32>, i32) #0411declare <32 x i32> @llvm.hexagon.V6.vrmpybus.acc.128B(<32 x i32>, <32 x i32>, i32) #0412declare <32 x i32> @llvm.hexagon.V6.vdmpybus.acc.128B(<32 x i32>, <32 x i32>, i32) #0413declare <64 x i32> @llvm.hexagon.V6.vdmpybus.dv.acc.128B(<64 x i32>, <64 x i32>, i32) #0414declare <32 x i32> @llvm.hexagon.V6.vdmpyhsusat.acc.128B(<32 x i32>, <32 x i32>, i32) #0415declare <32 x i32> @llvm.hexagon.V6.vdmpyhsuisat.acc.128B(<32 x i32>, <64 x i32>, i32) #0416declare <32 x i32> @llvm.hexagon.V6.vdmpyhisat.acc.128B(<32 x i32>, <64 x i32>, i32) #0417declare <32 x i32> @llvm.hexagon.V6.vdmpyhsat.acc.128B(<32 x i32>, <32 x i32>, i32) #0418declare <64 x i32> @llvm.hexagon.V6.vdmpyhb.dv.acc.128B(<64 x i32>, <64 x i32>, i32) #0419declare <64 x i32> @llvm.hexagon.V6.vmpybus.acc.128B(<64 x i32>, <32 x i32>, i32) #0420declare <64 x i32> @llvm.hexagon.V6.vmpabus.acc.128B(<64 x i32>, <64 x i32>, i32) #0421declare <64 x i32> @llvm.hexagon.V6.vmpahb.acc.128B(<64 x i32>, <64 x i32>, i32) #0422declare <64 x i32> @llvm.hexagon.V6.vmpyhsat.acc.128B(<64 x i32>, <32 x i32>, i32) #0423declare <64 x i32> @llvm.hexagon.V6.vmpyuh.acc.128B(<64 x i32>, <32 x i32>, i32) #0424declare <32 x i32> @llvm.hexagon.V6.vmpyiwb.acc.128B(<32 x i32>, <32 x i32>, i32) #0425declare <32 x i32> @llvm.hexagon.V6.vmpyiwh.acc.128B(<32 x i32>, <32 x i32>, i32) #0426declare <64 x i32> @llvm.hexagon.V6.vdsaduh.acc.128B(<64 x i32>, <64 x i32>, i32) #0427declare <32 x i32> @llvm.hexagon.V6.vmpyihb.acc.128B(<32 x i32>, <32 x i32>, i32) #0428declare <32 x i32> @llvm.hexagon.V6.vaslw.acc.128B(<32 x i32>, <32 x i32>, i32) #0429declare <32 x i32> @llvm.hexagon.V6.vasrw.acc.128B(<32 x i32>, <32 x i32>, i32) #0430declare <64 x i32> @llvm.hexagon.V6.vmpyub.acc.128B(<64 x i32>, <32 x i32>, i32) #0431 432attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }433