518 lines · plain
1; RUN: llc -mtriple=hexagon < %s | FileCheck %s2 3@c = external global <32 x i32>4@d = external global <16 x i32>5 6; CHECK-LABEL: test1:7; CHECK: v{{[0-9]+}}:{{[0-9]+}}.h = vtmpy(v{{[0-9]+}}:{{[0-9]+}}.b,r{{[0-9]+}}.b)8define void @test1(<32 x i32> %a, i32 %b) #0 {9entry:10 %0 = tail call <32 x i32> @llvm.hexagon.V6.vtmpyb(<32 x i32> %a, i32 %b)11 store <32 x i32> %0, ptr @c, align 12812 ret void13}14 15; CHECK-LABEL: test2:16; CHECK: v{{[0-9]+}}:{{[0-9]+}}.h = vtmpy(v{{[0-9]+}}:{{[0-9]+}}.ub,r{{[0-9]+}}.b)17define void @test2(<32 x i32> %a, i32 %b) #0 {18entry:19 %0 = tail call <32 x i32> @llvm.hexagon.V6.vtmpybus(<32 x i32> %a, i32 %b)20 store <32 x i32> %0, ptr @c, align 12821 ret void22}23 24; CHECK-LABEL: test3:25; CHECK: v{{[0-9]+}}.w = vdmpy(v{{[0-9]+}}.h,r{{[0-9]+}}.b)26define void @test3(<16 x i32> %a, i32 %b) #0 {27entry:28 %0 = tail call <16 x i32> @llvm.hexagon.V6.vdmpyhb(<16 x i32> %a, i32 %b)29 store <16 x i32> %0, ptr @d, align 6430 ret void31}32 33; CHECK-LABEL: test4:34; CHECK: v{{[0-9]+}}.uw = vrmpy(v{{[0-9]+}}.ub,r{{[0-9]+}}.ub)35define void @test4(<16 x i32> %a, i32 %b) #0 {36entry:37 %0 = tail call <16 x i32> @llvm.hexagon.V6.vrmpyub(<16 x i32> %a, i32 %b)38 store <16 x i32> %0, ptr @d, align 6439 ret void40}41 42; CHECK-LABEL: test5:43; CHECK: v{{[0-9]+}}.w = vrmpy(v{{[0-9]+}}.ub,r{{[0-9]+}}.b)44define void @test5(<16 x i32> %a, i32 %b) #0 {45entry:46 %0 = tail call <16 x i32> @llvm.hexagon.V6.vrmpybus(<16 x i32> %a, i32 %b)47 store <16 x i32> %0, ptr @d, align 6448 ret void49}50 51; CHECK-LABEL: test6:52; CHECK: v{{[0-9]+}}:{{[0-9]+}}.uw = vdsad(v{{[0-9]+}}:{{[0-9]+}}.uh,r{{[0-9]+}}.uh)53define void @test6(<32 x i32> %a, i32 %b) #0 {54entry:55 %0 = tail call <32 x i32> @llvm.hexagon.V6.vdsaduh(<32 x i32> %a, i32 %b)56 store <32 x i32> %0, ptr @c, align 12857 ret void58}59 60; CHECK-LABEL: test7:61; CHECK: v{{[0-9]+}}.h = vdmpy(v{{[0-9]+}}.ub,r{{[0-9]+}}.b)62define void @test7(<16 x i32> %a, i32 %b) #0 {63entry:64 %0 = tail call <16 x i32> @llvm.hexagon.V6.vdmpybus(<16 x i32> %a, i32 %b)65 store <16 x i32> %0, ptr @d, align 6466 ret void67}68 69; CHECK-LABEL: test8:70; CHECK: v{{[0-9]+}}:{{[0-9]+}}.h = vdmpy(v{{[0-9]+}}:{{[0-9]+}}.ub,r{{[0-9]+}}.b)71define void @test8(<32 x i32> %a, i32 %b) #0 {72entry:73 %0 = tail call <32 x i32> @llvm.hexagon.V6.vdmpybus.dv(<32 x i32> %a, i32 %b)74 store <32 x i32> %0, ptr @c, align 12875 ret void76}77 78; CHECK-LABEL: test9:79; CHECK: v{{[0-9]+}}.w = vdmpy(v{{[0-9]+}}.h,r{{[0-9]+}}.uh):sat80define void @test9(<16 x i32> %a, i32 %b) #0 {81entry:82 %0 = tail call <16 x i32> @llvm.hexagon.V6.vdmpyhsusat(<16 x i32> %a, i32 %b)83 store <16 x i32> %0, ptr @d, align 6484 ret void85}86 87; CHECK-LABEL: test10:88; CHECK: v{{[0-9]+}}.w = vdmpy(v{{[0-9]+}}:{{[0-9]+}}.h,r{{[0-9]+}}.uh,#1):sat89define void @test10(<32 x i32> %a, i32 %b) #0 {90entry:91 %0 = tail call <16 x i32> @llvm.hexagon.V6.vdmpyhsuisat(<32 x i32> %a, i32 %b)92 store <16 x i32> %0, ptr @d, align 6493 ret void94}95 96; CHECK-LABEL: test11:97; CHECK: v{{[0-9]+}}.w = vdmpy(v{{[0-9]+}}.h,r{{[0-9]+}}.h):sat98define void @test11(<16 x i32> %a, i32 %b) #0 {99entry:100 %0 = tail call <16 x i32> @llvm.hexagon.V6.vdmpyhsat(<16 x i32> %a, i32 %b)101 store <16 x i32> %0, ptr @d, align 64102 ret void103}104 105; CHECK-LABEL: test12:106; CHECK: v{{[0-9]+}}.w = vdmpy(v{{[0-9]+}}:{{[0-9]+}}.h,r{{[0-9]+}}.h):sat107define void @test12(<32 x i32> %a, i32 %b) #0 {108entry:109 %0 = tail call <16 x i32> @llvm.hexagon.V6.vdmpyhisat(<32 x i32> %a, i32 %b)110 store <16 x i32> %0, ptr @d, align 64111 ret void112}113 114; CHECK-LABEL: test13:115; CHECK: v{{[0-9]+}}:{{[0-9]+}}.w = vdmpy(v{{[0-9]+}}:{{[0-9]+}}.h,r{{[0-9]+}}.b)116define void @test13(<32 x i32> %a, i32 %b) #0 {117entry:118 %0 = tail call <32 x i32> @llvm.hexagon.V6.vdmpyhb.dv(<32 x i32> %a, i32 %b)119 store <32 x i32> %0, ptr @c, align 128120 ret void121}122 123; CHECK-LABEL: test14:124; CHECK: v{{[0-9]+}}:{{[0-9]+}}.h = vmpy(v{{[0-9]+}}.ub,r{{[0-9]+}}.b)125define void @test14(<16 x i32> %a, i32 %b) #0 {126entry:127 %0 = tail call <32 x i32> @llvm.hexagon.V6.vmpybus(<16 x i32> %a, i32 %b)128 store <32 x i32> %0, ptr @c, align 128129 ret void130}131 132; CHECK-LABEL: test15:133; CHECK: v{{[0-9]+}}:{{[0-9]+}}.h = vmpa(v{{[0-9]+}}:{{[0-9]+}}.ub,r{{[0-9]+}}.b)134define void @test15(<32 x i32> %a, i32 %b) #0 {135entry:136 %0 = tail call <32 x i32> @llvm.hexagon.V6.vmpabus(<32 x i32> %a, i32 %b)137 store <32 x i32> %0, ptr @c, align 128138 ret void139}140 141; CHECK-LABEL: test16:142; CHECK: v{{[0-9]+}}:{{[0-9]+}}.w = vmpa(v{{[0-9]+}}:{{[0-9]+}}.h,r{{[0-9]+}}.b)143define void @test16(<32 x i32> %a, i32 %b) #0 {144entry:145 %0 = tail call <32 x i32> @llvm.hexagon.V6.vmpahb(<32 x i32> %a, i32 %b)146 store <32 x i32> %0, ptr @c, align 128147 ret void148}149 150; CHECK-LABEL: test17:151; CHECK: v{{[0-9]+}}:{{[0-9]+}}.w = vmpy(v{{[0-9]+}}.h,r{{[0-9]+}}.h)152define void @test17(<16 x i32> %a, i32 %b) #0 {153entry:154 %0 = tail call <32 x i32> @llvm.hexagon.V6.vmpyh(<16 x i32> %a, i32 %b)155 store <32 x i32> %0, ptr @c, align 128156 ret void157}158 159; CHECK-LABEL: test18:160; CHECK: v{{[0-9]+}}.h = vmpy(v{{[0-9]+}}.h,r{{[0-9]+}}.h):<<1:sat161define void @test18(<16 x i32> %a, i32 %b) #0 {162entry:163 %0 = tail call <16 x i32> @llvm.hexagon.V6.vmpyhss(<16 x i32> %a, i32 %b)164 store <16 x i32> %0, ptr @d, align 64165 ret void166}167 168; CHECK-LABEL: test19:169; CHECK: v{{[0-9]+}}.h = vmpy(v{{[0-9]+}}.h,r{{[0-9]+}}.h):<<1:rnd:sat170define void @test19(<16 x i32> %a, i32 %b) #0 {171entry:172 %0 = tail call <16 x i32> @llvm.hexagon.V6.vmpyhsrs(<16 x i32> %a, i32 %b)173 store <16 x i32> %0, ptr @d, align 64174 ret void175}176 177; CHECK-LABEL: test20:178; CHECK: v{{[0-9]+}}:{{[0-9]+}}.uw = vmpy(v{{[0-9]+}}.uh,r{{[0-9]+}}.uh)179define void @test20(<16 x i32> %a, i32 %b) #0 {180entry:181 %0 = tail call <32 x i32> @llvm.hexagon.V6.vmpyuh(<16 x i32> %a, i32 %b)182 store <32 x i32> %0, ptr @c, align 128183 ret void184}185 186; CHECK-LABEL: test21:187; CHECK: v{{[0-9]+}}.h = vmpyi(v{{[0-9]+}}.h,r{{[0-9]+}}.b)188define void @test21(<16 x i32> %a, i32 %b) #0 {189entry:190 %0 = tail call <16 x i32> @llvm.hexagon.V6.vmpyihb(<16 x i32> %a, i32 %b)191 store <16 x i32> %0, ptr @d, align 64192 ret void193}194 195; CHECK-LABEL: test22:196; CHECK: v{{[0-9]+}} = vror(v{{[0-9]+}},r{{[0-9]+}})197define void @test22(<16 x i32> %a, i32 %b) #0 {198entry:199 %0 = tail call <16 x i32> @llvm.hexagon.V6.vror(<16 x i32> %a, i32 %b)200 store <16 x i32> %0, ptr @d, align 64201 ret void202}203 204; CHECK-LABEL: test23:205; CHECK: v{{[0-9]+}}.w = vasr(v{{[0-9]+}}.w,r{{[0-9]+}})206define void @test23(<16 x i32> %a, i32 %b) #0 {207entry:208 %0 = tail call <16 x i32> @llvm.hexagon.V6.vasrw(<16 x i32> %a, i32 %b)209 store <16 x i32> %0, ptr @d, align 64210 ret void211}212 213; CHECK-LABEL: test24:214; CHECK: v{{[0-9]+}}.h = vasr(v{{[0-9]+}}.h,r{{[0-9]+}})215define void @test24(<16 x i32> %a, i32 %b) #0 {216entry:217 %0 = tail call <16 x i32> @llvm.hexagon.V6.vasrh(<16 x i32> %a, i32 %b)218 store <16 x i32> %0, ptr @d, align 64219 ret void220}221 222; CHECK-LABEL: test25:223; CHECK: v{{[0-9]+}}.w = vasl(v{{[0-9]+}}.w,r{{[0-9]+}})224define void @test25(<16 x i32> %a, i32 %b) #0 {225entry:226 %0 = tail call <16 x i32> @llvm.hexagon.V6.vaslw(<16 x i32> %a, i32 %b)227 store <16 x i32> %0, ptr @d, align 64228 ret void229}230 231; CHECK-LABEL: test26:232; CHECK: v{{[0-9]+}}.h = vasl(v{{[0-9]+}}.h,r{{[0-9]+}})233define void @test26(<16 x i32> %a, i32 %b) #0 {234entry:235 %0 = tail call <16 x i32> @llvm.hexagon.V6.vaslh(<16 x i32> %a, i32 %b)236 store <16 x i32> %0, ptr @d, align 64237 ret void238}239 240; CHECK-LABEL: test27:241; CHECK: v{{[0-9]+}}.uw = vlsr(v{{[0-9]+}}.uw,r{{[0-9]+}})242define void @test27(<16 x i32> %a, i32 %b) #0 {243entry:244 %0 = tail call <16 x i32> @llvm.hexagon.V6.vlsrw(<16 x i32> %a, i32 %b)245 store <16 x i32> %0, ptr @d, align 64246 ret void247}248 249; CHECK-LABEL: test28:250; CHECK: v{{[0-9]+}}.uh = vlsr(v{{[0-9]+}}.uh,r{{[0-9]+}})251define void @test28(<16 x i32> %a, i32 %b) #0 {252entry:253 %0 = tail call <16 x i32> @llvm.hexagon.V6.vlsrh(<16 x i32> %a, i32 %b)254 store <16 x i32> %0, ptr @d, align 64255 ret void256}257 258; CHECK-LABEL: test29:259; CHECK: v{{[0-9]+}}.w = vmpyi(v{{[0-9]+}}.w,r{{[0-9]+}}.h)260define void @test29(<16 x i32> %a, i32 %b) #0 {261entry:262 %0 = tail call <16 x i32> @llvm.hexagon.V6.vmpyiwh(<16 x i32> %a, i32 %b)263 store <16 x i32> %0, ptr @d, align 64264 ret void265}266 267; CHECK-LABEL: test30:268; CHECK: v{{[0-9]+}}.w = vmpyi(v{{[0-9]+}}.w,r{{[0-9]+}}.b)269define void @test30(<16 x i32> %a, i32 %b) #0 {270entry:271 %0 = tail call <16 x i32> @llvm.hexagon.V6.vmpyiwb(<16 x i32> %a, i32 %b)272 store <16 x i32> %0, ptr @d, align 64273 ret void274}275 276; CHECK-LABEL: test31:277; CHECK: v{{[0-9]+}}:{{[0-9]+}}.w = vtmpy(v{{[0-9]+}}:{{[0-9]+}}.h,r{{[0-9]+}}.b)278define void @test31(<32 x i32> %a, i32 %b) #0 {279entry:280 %0 = tail call <32 x i32> @llvm.hexagon.V6.vtmpyhb(<32 x i32> %a, i32 %b)281 store <32 x i32> %0, ptr @c, align 128282 ret void283}284 285; CHECK-LABEL: test32:286; CHECK: v{{[0-9]+}}:{{[0-9]+}}.uh = vmpy(v{{[0-9]+}}.ub,r{{[0-9]+}}.ub)287define void @test32(<16 x i32> %a, i32 %b) #0 {288entry:289 %0 = tail call <32 x i32> @llvm.hexagon.V6.vmpyub(<16 x i32> %a, i32 %b)290 store <32 x i32> %0, ptr @c, align 128291 ret void292}293 294; CHECK-LABEL: test33:295; CHECK: v{{[0-9]+}}.uw = vrmpy(v{{[0-9]+}}.ub,v{{[0-9]+}}.ub)296define void @test33(<16 x i32> %a, <16 x i32> %b) #0 {297entry:298 %0 = tail call <16 x i32> @llvm.hexagon.V6.vrmpyubv(<16 x i32> %a, <16 x i32> %b)299 store <16 x i32> %0, ptr @d, align 64300 ret void301}302 303; CHECK-LABEL: test34:304; CHECK: v{{[0-9]+}}.w = vrmpy(v{{[0-9]+}}.b,v{{[0-9]+}}.b)305define void @test34(<16 x i32> %a, <16 x i32> %b) #0 {306entry:307 %0 = tail call <16 x i32> @llvm.hexagon.V6.vrmpybv(<16 x i32> %a, <16 x i32> %b)308 store <16 x i32> %0, ptr @d, align 64309 ret void310}311 312; CHECK-LABEL: test35:313; CHECK: v{{[0-9]+}}.w = vrmpy(v{{[0-9]+}}.ub,v{{[0-9]+}}.b)314define void @test35(<16 x i32> %a, <16 x i32> %b) #0 {315entry:316 %0 = tail call <16 x i32> @llvm.hexagon.V6.vrmpybusv(<16 x i32> %a, <16 x i32> %b)317 store <16 x i32> %0, ptr @d, align 64318 ret void319}320 321; CHECK-LABEL: test36:322; CHECK: v{{[0-9]+}}.w = vdmpy(v{{[0-9]+}}.h,v{{[0-9]+}}.h):sat323define void @test36(<16 x i32> %a, <16 x i32> %b) #0 {324entry:325 %0 = tail call <16 x i32> @llvm.hexagon.V6.vdmpyhvsat(<16 x i32> %a, <16 x i32> %b)326 store <16 x i32> %0, ptr @d, align 64327 ret void328}329 330; CHECK-LABEL: test37:331; CHECK: v{{[0-9]+}}:{{[0-9]+}}.h = vmpy(v{{[0-9]+}}.b,v{{[0-9]+}}.b)332define void @test37(<16 x i32> %a, <16 x i32> %b) #0 {333entry:334 %0 = tail call <32 x i32> @llvm.hexagon.V6.vmpybv(<16 x i32> %a, <16 x i32> %b)335 store <32 x i32> %0, ptr @c, align 128336 ret void337}338 339; CHECK-LABEL: test38:340; CHECK: v{{[0-9]+}}:{{[0-9]+}}.uh = vmpy(v{{[0-9]+}}.ub,v{{[0-9]+}}.ub)341define void @test38(<16 x i32> %a, <16 x i32> %b) #0 {342entry:343 %0 = tail call <32 x i32> @llvm.hexagon.V6.vmpyubv(<16 x i32> %a, <16 x i32> %b)344 store <32 x i32> %0, ptr @c, align 128345 ret void346}347 348; CHECK-LABEL: test39:349; CHECK: v{{[0-9]+}}:{{[0-9]+}}.h = vmpy(v{{[0-9]+}}.ub,v{{[0-9]+}}.b)350define void @test39(<16 x i32> %a, <16 x i32> %b) #0 {351entry:352 %0 = tail call <32 x i32> @llvm.hexagon.V6.vmpybusv(<16 x i32> %a, <16 x i32> %b)353 store <32 x i32> %0, ptr @c, align 128354 ret void355}356 357; CHECK-LABEL: test40:358; CHECK: v{{[0-9]+}}:{{[0-9]+}}.w = vmpy(v{{[0-9]+}}.h,v{{[0-9]+}}.h)359define void @test40(<16 x i32> %a, <16 x i32> %b) #0 {360entry:361 %0 = tail call <32 x i32> @llvm.hexagon.V6.vmpyhv(<16 x i32> %a, <16 x i32> %b)362 store <32 x i32> %0, ptr @c, align 128363 ret void364}365 366; CHECK-LABEL: test41:367; CHECK: v{{[0-9]+}}:{{[0-9]+}}.uw = vmpy(v{{[0-9]+}}.uh,v{{[0-9]+}}.uh)368define void @test41(<16 x i32> %a, <16 x i32> %b) #0 {369entry:370 %0 = tail call <32 x i32> @llvm.hexagon.V6.vmpyuhv(<16 x i32> %a, <16 x i32> %b)371 store <32 x i32> %0, ptr @c, align 128372 ret void373}374 375; CHECK-LABEL: test42:376; CHECK: v{{[0-9]+}}.h = vmpy(v{{[0-9]+}}.h,v{{[0-9]+}}.h):<<1:rnd:sat377define void @test42(<16 x i32> %a, <16 x i32> %b) #0 {378entry:379 %0 = tail call <16 x i32> @llvm.hexagon.V6.vmpyhvsrs(<16 x i32> %a, <16 x i32> %b)380 store <16 x i32> %0, ptr @d, align 64381 ret void382}383 384; CHECK-LABEL: test43:385; CHECK: v{{[0-9]+}}:{{[0-9]+}}.w = vmpy(v{{[0-9]+}}.h,v{{[0-9]+}}.uh)386define void @test43(<16 x i32> %a, <16 x i32> %b) #0 {387entry:388 %0 = tail call <32 x i32> @llvm.hexagon.V6.vmpyhus(<16 x i32> %a, <16 x i32> %b)389 store <32 x i32> %0, ptr @c, align 128390 ret void391}392 393; CHECK-LABEL: test44:394; CHECK: v{{[0-9]+}}:{{[0-9]+}}.h = vmpa(v{{[0-9]+}}:{{[0-9]+}}.ub,v{{[0-9]+}}:{{[0-9]+}}.b)395define void @test44(<32 x i32> %a, <32 x i32> %b) #0 {396entry:397 %0 = tail call <32 x i32> @llvm.hexagon.V6.vmpabusv(<32 x i32> %a, <32 x i32> %b)398 store <32 x i32> %0, ptr @c, align 128399 ret void400}401 402; CHECK-LABEL: test45:403; CHECK: v{{[0-9]+}}.h = vmpyi(v{{[0-9]+}}.h,v{{[0-9]+}}.h)404define void @test45(<16 x i32> %a, <16 x i32> %b) #0 {405entry:406 %0 = tail call <16 x i32> @llvm.hexagon.V6.vmpyih(<16 x i32> %a, <16 x i32> %b)407 store <16 x i32> %0, ptr @d, align 64408 ret void409}410 411; CHECK-LABEL: test46:412; CHECK: v{{[0-9]+}}.w = vmpye(v{{[0-9]+}}.w,v{{[0-9]+}}.uh)413define void @test46(<16 x i32> %a, <16 x i32> %b) #0 {414entry:415 %0 = tail call <16 x i32> @llvm.hexagon.V6.vmpyewuh(<16 x i32> %a, <16 x i32> %b)416 store <16 x i32> %0, ptr @d, align 64417 ret void418}419 420; CHECK-LABEL: test47:421; CHECK: v{{[0-9]+}}.w = vmpyo(v{{[0-9]+}}.w,v{{[0-9]+}}.h):<<1:sat422define void @test47(<16 x i32> %a, <16 x i32> %b) #0 {423entry:424 %0 = tail call <16 x i32> @llvm.hexagon.V6.vmpyowh(<16 x i32> %a, <16 x i32> %b)425 store <16 x i32> %0, ptr @d, align 64426 ret void427}428 429; CHECK-LABEL: test48:430; CHECK: v{{[0-9]+}}.w = vmpyie(v{{[0-9]+}}.w,v{{[0-9]+}}.uh)431define void @test48(<16 x i32> %a, <16 x i32> %b) #0 {432entry:433 %0 = tail call <16 x i32> @llvm.hexagon.V6.vmpyiewuh(<16 x i32> %a, <16 x i32> %b)434 store <16 x i32> %0, ptr @d, align 64435 ret void436}437 438; CHECK-LABEL: test49:439; CHECK: v{{[0-9]+}}.w = vmpyio(v{{[0-9]+}}.w,v{{[0-9]+}}.h)440define void @test49(<16 x i32> %a, <16 x i32> %b) #0 {441entry:442 %0 = tail call <16 x i32> @llvm.hexagon.V6.vmpyiowh(<16 x i32> %a, <16 x i32> %b)443 store <16 x i32> %0, ptr @d, align 64444 ret void445}446 447; CHECK-LABEL: test50:448; CHECK: v{{[0-9]+}}.w = vmpyo(v{{[0-9]+}}.w,v{{[0-9]+}}.h):<<1:rnd:sat449define void @test50(<16 x i32> %a, <16 x i32> %b) #0 {450entry:451 %0 = tail call <16 x i32> @llvm.hexagon.V6.vmpyowh.rnd(<16 x i32> %a, <16 x i32> %b)452 store <16 x i32> %0, ptr @d, align 64453 ret void454}455 456; CHECK-LABEL: test51:457; CHECK: v{{[0-9]+}}.w = vmpyieo(v{{[0-9]+}}.h,v{{[0-9]+}}.h)458define void @test51(<16 x i32> %a, <16 x i32> %b) #0 {459entry:460 %0 = tail call <16 x i32> @llvm.hexagon.V6.vmpyieoh(<16 x i32> %a, <16 x i32> %b)461 store <16 x i32> %0, ptr @d, align 64462 ret void463}464 465declare <32 x i32> @llvm.hexagon.V6.vtmpyb(<32 x i32>, i32) #0466declare <32 x i32> @llvm.hexagon.V6.vtmpybus(<32 x i32>, i32) #0467declare <16 x i32> @llvm.hexagon.V6.vdmpyhb(<16 x i32>, i32) #0468declare <16 x i32> @llvm.hexagon.V6.vrmpyub(<16 x i32>, i32) #0469declare <16 x i32> @llvm.hexagon.V6.vrmpybus(<16 x i32>, i32) #0470declare <32 x i32> @llvm.hexagon.V6.vdsaduh(<32 x i32>, i32) #0471declare <16 x i32> @llvm.hexagon.V6.vdmpybus(<16 x i32>, i32) #0472declare <32 x i32> @llvm.hexagon.V6.vdmpybus.dv(<32 x i32>, i32) #0473declare <16 x i32> @llvm.hexagon.V6.vdmpyhsusat(<16 x i32>, i32) #0474declare <16 x i32> @llvm.hexagon.V6.vdmpyhsuisat(<32 x i32>, i32) #0475declare <16 x i32> @llvm.hexagon.V6.vdmpyhsat(<16 x i32>, i32) #0476declare <16 x i32> @llvm.hexagon.V6.vdmpyhisat(<32 x i32>, i32) #0477declare <32 x i32> @llvm.hexagon.V6.vdmpyhb.dv(<32 x i32>, i32) #0478declare <32 x i32> @llvm.hexagon.V6.vmpybus(<16 x i32>, i32) #0479declare <32 x i32> @llvm.hexagon.V6.vmpabus(<32 x i32>, i32) #0480declare <32 x i32> @llvm.hexagon.V6.vmpahb(<32 x i32>, i32) #0481declare <32 x i32> @llvm.hexagon.V6.vmpyh(<16 x i32>, i32) #0482declare <16 x i32> @llvm.hexagon.V6.vmpyhss(<16 x i32>, i32) #0483declare <16 x i32> @llvm.hexagon.V6.vmpyhsrs(<16 x i32>, i32) #0484declare <32 x i32> @llvm.hexagon.V6.vmpyuh(<16 x i32>, i32) #0485declare <16 x i32> @llvm.hexagon.V6.vmpyihb(<16 x i32>, i32) #0486declare <16 x i32> @llvm.hexagon.V6.vror(<16 x i32>, i32) #0487declare <16 x i32> @llvm.hexagon.V6.vasrw(<16 x i32>, i32) #0488declare <16 x i32> @llvm.hexagon.V6.vasrh(<16 x i32>, i32) #0489declare <16 x i32> @llvm.hexagon.V6.vaslw(<16 x i32>, i32) #0490declare <16 x i32> @llvm.hexagon.V6.vaslh(<16 x i32>, i32) #0491declare <16 x i32> @llvm.hexagon.V6.vlsrw(<16 x i32>, i32) #0492declare <16 x i32> @llvm.hexagon.V6.vlsrh(<16 x i32>, i32) #0493declare <16 x i32> @llvm.hexagon.V6.vmpyiwh(<16 x i32>, i32) #0494declare <16 x i32> @llvm.hexagon.V6.vmpyiwb(<16 x i32>, i32) #0495declare <32 x i32> @llvm.hexagon.V6.vtmpyhb(<32 x i32>, i32) #0496declare <32 x i32> @llvm.hexagon.V6.vmpyub(<16 x i32>, i32) #0497declare <16 x i32> @llvm.hexagon.V6.vrmpyubv(<16 x i32>, <16 x i32>) #0498declare <16 x i32> @llvm.hexagon.V6.vrmpybv(<16 x i32>, <16 x i32>) #0499declare <16 x i32> @llvm.hexagon.V6.vrmpybusv(<16 x i32>, <16 x i32>) #0500declare <16 x i32> @llvm.hexagon.V6.vdmpyhvsat(<16 x i32>, <16 x i32>) #0501declare <32 x i32> @llvm.hexagon.V6.vmpybv(<16 x i32>, <16 x i32>) #0502declare <32 x i32> @llvm.hexagon.V6.vmpyubv(<16 x i32>, <16 x i32>) #0503declare <32 x i32> @llvm.hexagon.V6.vmpybusv(<16 x i32>, <16 x i32>) #0504declare <32 x i32> @llvm.hexagon.V6.vmpyhv(<16 x i32>, <16 x i32>) #0505declare <32 x i32> @llvm.hexagon.V6.vmpyuhv(<16 x i32>, <16 x i32>) #0506declare <16 x i32> @llvm.hexagon.V6.vmpyhvsrs(<16 x i32>, <16 x i32>) #0507declare <32 x i32> @llvm.hexagon.V6.vmpyhus(<16 x i32>, <16 x i32>) #0508declare <32 x i32> @llvm.hexagon.V6.vmpabusv(<32 x i32>, <32 x i32>) #0509declare <16 x i32> @llvm.hexagon.V6.vmpyih(<16 x i32>, <16 x i32>) #0510declare <16 x i32> @llvm.hexagon.V6.vmpyewuh(<16 x i32>, <16 x i32>) #0511declare <16 x i32> @llvm.hexagon.V6.vmpyowh(<16 x i32>, <16 x i32>) #0512declare <16 x i32> @llvm.hexagon.V6.vmpyiewuh(<16 x i32>, <16 x i32>) #0513declare <16 x i32> @llvm.hexagon.V6.vmpyiowh(<16 x i32>, <16 x i32>) #0514declare <16 x i32> @llvm.hexagon.V6.vmpyowh.rnd(<16 x i32>, <16 x i32>) #0515declare <16 x i32> @llvm.hexagon.V6.vmpyieoh(<16 x i32>, <16 x i32>) #0516 517attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }518