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1; RUN: llc -mtriple=hexagon < %s | FileCheck %s2;3; Check that the resulting register pair has the registers in the right order.4 5; CHECK: vdeal6; CHECK: vdeal7; CHECK: v[[V1:[0-9]+]]:[[V0:[0-9]+]] = vshuff8; CHECK-NEXT: }9; CHECK-NEXT: {10; CHECK-NEXT: vmem(r[[RA:[0-9]+]]+#0) = v[[V0]]11; CHECK-NEXT: }12; CHECK-NEXT: {13; CHECK-NEXT: r0 = memw(r1+#0)14; CHECK-NEXT: }15; CHECK-NEXT: {16; CHECK-NEXT: r1 = memw(r1+#4)17; CHECK-NEXT: }18; CHECK-NEXT: {19; CHECK-NEXT: r31:30 = dealloc_return(r30):raw20; CHECK-NEXT: }21 22define i64 @foo(<64 x i16> %a0, <64 x i16> %a1) #0 {23 %v0 = icmp ugt <64 x i16> %a0, %a124 %v1 = bitcast <64 x i1> %v0 to i6425 ret i64 %v126}27 28attributes #0 = { nounwind readnone "target-cpu"="hexagonv66" "target-features"="+hvx,+hvx-length128b,-packets" }29 30