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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=hexagon < %s | FileCheck %s3 4define void @f0(ptr %a0, i32 %a1, i32 %a2) #0 {5; CHECK-LABEL: f0:6; CHECK: // %bb.0:7; CHECK-NEXT: {8; CHECK-NEXT: p0 = tstbit(r1,#0)9; CHECK-NEXT: }10; CHECK-NEXT: {11; CHECK-NEXT: r2 = asl(r2,#2)12; CHECK-NEXT: }13; CHECK-NEXT: {14; CHECK-NEXT: r4 = memub(r0+#0)15; CHECK-NEXT: }16; CHECK-NEXT: {17; CHECK-NEXT: r3 = #418; CHECK-NEXT: }19; CHECK-NEXT: {20; CHECK-NEXT: r1 = mux(p0,#-1,#0)21; CHECK-NEXT: }22; CHECK-NEXT: {23; CHECK-NEXT: r4 = insert(r1,r3:2)24; CHECK-NEXT: }25; CHECK-NEXT: {26; CHECK-NEXT: r1 = and(r4,#255)27; CHECK-NEXT: }28; CHECK-NEXT: {29; CHECK-NEXT: memb(r0+#0) = r130; CHECK-NEXT: }31; CHECK-NEXT: {32; CHECK-NEXT: jumpr r3133; CHECK-NEXT: }34 %v0 = load <2 x i1>, ptr %a035 %v1 = trunc i32 %a1 to i136 %v2 = insertelement <2 x i1> %v0, i1 %v1, i32 %a237 store <2 x i1> %v2, ptr %a038 ret void39}40 41define void @f1(ptr %a0, i32 %a1, i32 %a2) #0 {42; CHECK-LABEL: f1:43; CHECK: // %bb.0:44; CHECK-NEXT: {45; CHECK-NEXT: p0 = tstbit(r1,#0)46; CHECK-NEXT: }47; CHECK-NEXT: {48; CHECK-NEXT: r2 = asl(r2,#1)49; CHECK-NEXT: }50; CHECK-NEXT: {51; CHECK-NEXT: r4 = memub(r0+#0)52; CHECK-NEXT: }53; CHECK-NEXT: {54; CHECK-NEXT: r3 = #255; CHECK-NEXT: }56; CHECK-NEXT: {57; CHECK-NEXT: r1 = mux(p0,#-1,#0)58; CHECK-NEXT: }59; CHECK-NEXT: {60; CHECK-NEXT: r4 = insert(r1,r3:2)61; CHECK-NEXT: }62; CHECK-NEXT: {63; CHECK-NEXT: r1 = and(r4,#255)64; CHECK-NEXT: }65; CHECK-NEXT: {66; CHECK-NEXT: memb(r0+#0) = r167; CHECK-NEXT: }68; CHECK-NEXT: {69; CHECK-NEXT: jumpr r3170; CHECK-NEXT: }71 %v0 = load <4 x i1>, ptr %a072 %v1 = trunc i32 %a1 to i173 %v2 = insertelement <4 x i1> %v0, i1 %v1, i32 %a274 store <4 x i1> %v2, ptr %a075 ret void76}77 78define void @f2(ptr %a0, i32 %a1, i32 %a2) #0 {79; CHECK-LABEL: f2:80; CHECK: // %bb.0:81; CHECK-NEXT: {82; CHECK-NEXT: p0 = tstbit(r1,#0)83; CHECK-NEXT: }84; CHECK-NEXT: {85; CHECK-NEXT: r6 = memub(r0+#0)86; CHECK-NEXT: }87; CHECK-NEXT: {88; CHECK-NEXT: r3 = #189; CHECK-NEXT: }90; CHECK-NEXT: {91; CHECK-NEXT: r4 = mux(p0,#-1,#0)92; CHECK-NEXT: }93; CHECK-NEXT: {94; CHECK-NEXT: r6 = insert(r4,r3:2)95; CHECK-NEXT: }96; CHECK-NEXT: {97; CHECK-NEXT: r1 = and(r6,#255)98; CHECK-NEXT: }99; CHECK-NEXT: {100; CHECK-NEXT: memb(r0+#0) = r1101; CHECK-NEXT: }102; CHECK-NEXT: {103; CHECK-NEXT: jumpr r31104; CHECK-NEXT: }105 %v0 = load <8 x i1>, ptr %a0106 %v1 = trunc i32 %a1 to i1107 %v2 = insertelement <8 x i1> %v0, i1 %v1, i32 %a2108 store <8 x i1> %v2, ptr %a0109 ret void110}111 112attributes #0 = { nounwind "target-features"="-packets" }113