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1; RUN: llc -mtriple=hexagon -hexagon-expand-condsets=0 < %s | FileCheck %s2 3; In the IR, the i1 value is zero-extended first, then passed to add.4; Check that in the final code, the mux happens after the add.5; CHECK: [[REG1:r[0-9]+]] = add([[REG0:r[0-9]+]],#1)6; CHECK: r{{[0-9]+}} = mux(p{{[0-3]}},[[REG1]],[[REG0]])7 8define i32 @foo(i32 %a, i32 %b) {9 %v0 = icmp eq i32 %a, %b10 %v1 = zext i1 %v0 to i3211 %v2 = add i32 %v1, %a12 ret i32 %v213}14