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1; Tests the conversion pattern for v64i1 to v64f162; r0, r3 and r9 registers are i32 types converted from3; v32i1 via a bitcasting sequence.4 5; RUN: llc -march=hexagon -mattr=+hvxv79,+hvx-length128b \6; RUN: %s -verify-machineinstrs -o - | FileCheck %s7 8; CHECK: [[V3:v[0-9]+]] = vsplat([[R0:r[0-9]+]])9; CHECK: [[Q0:q[0-9]+]] = vand([[V3]],[[R0]])10; CHECK: [[V4:v[0-9]+]].w = prefixsum([[Q0]])11; CHECK: [[V5:v[0-9]+]].w = vsub([[V4]].w,[[V3]].w)12; CHECK: [[V1:v[0-9]+]] = vsplat(r13; CHECK: [[V2:v[0-9]+]] = vsplat(r14; CHECK: [[V6:v[0-9]+]].w = vlsr([[V1]].w,[[V5]].w)15; CHECK: [[V7:v[0-9]+]].w = vlsr([[V2]].w,[[V5]].w)16; CHECK: [[V8:v[0-9]+]] = vand([[V6]],[[V3]])17; CHECK: [[V9:v[0-9]+]] = vand([[V7]],[[V3]])18; CHECK: [[V10:v[0-9]+]].h = vpacke([[V9]].w,[[V8]].w)19; CHECK: .hf = [[V10]].h20 21define <64 x half> @uitofp_i1(<64 x i16> %in0, <64 x i16> %in1)22{23 %in = icmp eq <64 x i16> %in0, %in124 %fp0 = uitofp <64 x i1> %in to <64 x half>25 %out = fadd <64 x half> %fp0, %fp026 ret <64 x half> %out27}28