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1; Check if extract_subvectors is handled properly in Hexagon backend when the2; the source vector is a vector-pair and result vector is not hvx vector size.3; https://github.com/llvm/llvm-project/issues/1287754;5; Example of such a case:6; ...7; t2: v64i32,ch = CopyFromReg t0, Register:v64i32 %08; t17: v2i32 = extract_subvector t2, Constant:i32<4>9; ...10 11; RUN: llc -mtriple=hexagon -mattr="hvx-length128b" < %s | FileCheck %s12 13; CHECK-LABEL: extract_subvec:14; CHECK: r29 = and(r29,#-128)15; CHECK: [[R1:r([0-9]+)]] = add(r29,#0)16; CHECK: vmem([[R1]]+#0) = v017; CHECK-DAG: r[[R4:[0-9]+]] = memw([[R1]]+#0)18; CHECK-DAG: r[[R5:[0-9]+]] = memw([[R1]]+#4)19; CHECK-DAG: r[[R6:[0-9]+]] = memw([[R1]]+#8)20; CHECK-DAG: r[[R7:[0-9]+]] = memw([[R1]]+#12)21; CHECK-DAG: r[[R8:[0-9]+]] = memw([[R1]]+#16)22; CHECK-DAG: r[[R9:[0-9]+]] = memw([[R1]]+#20)23; CHECK-DAG: r[[R2:[0-9]+]] = memw([[R1]]+#24)24; CHECK-DAG: r[[R3:[0-9]+]] = memw([[R1]]+#28)25; CHECK-DAG: memd(r0+#0) = r[[R5]]:[[R4]]26; CHECK-DAG: memd(r0+#8) = r[[R7]]:[[R6]]27; CHECK-DAG: memd(r0+#16) = r[[R9]]:[[R8]]28; CHECK-DAG: memw(r0+#24) = r[[R2]]29define void @extract_subvec(<56 x i32> %val, ptr %buf) {30entry:31 %split = shufflevector <56 x i32> %val, <56 x i32> zeroinitializer, <7 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6>32 store <7 x i32> %split, ptr %buf, align 3233 ret void34}35