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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=hexagon < %s | FileCheck %s3 4define <4 x i8> @f0(<4 x i8> %a0, <4 x i8> %a1) #0 {5; CHECK-LABEL: f0:6; CHECK: // %bb.0:7; CHECK-NEXT: {8; CHECK-NEXT: r2 = r19; CHECK-NEXT: }10; CHECK-NEXT: {11; CHECK-NEXT: r7:6 = combine(#0,#0)12; CHECK-NEXT: }13; CHECK-NEXT: {14; CHECK-NEXT: r5:4 = vmpybu(r0,r1)15; CHECK-NEXT: }16; CHECK-NEXT: {17; CHECK-NEXT: p1 = vcmpb.gt(r1:0,#-1)18; CHECK-NEXT: }19; CHECK-NEXT: {20; CHECK-NEXT: p0 = vcmpb.gt(r3:2,#-1)21; CHECK-NEXT: }22; CHECK-NEXT: {23; CHECK-NEXT: r3:2 = vmux(p1,r7:6,r3:2)24; CHECK-NEXT: }25; CHECK-NEXT: {26; CHECK-NEXT: r1:0 = vmux(p0,r7:6,r1:0)27; CHECK-NEXT: }28; CHECK-NEXT: {29; CHECK-NEXT: r4 = vtrunohb(r5:4)30; CHECK-NEXT: }31; CHECK-NEXT: {32; CHECK-NEXT: r7:6 = vmpybu(r0,r0)33; CHECK-NEXT: }34; CHECK-NEXT: {35; CHECK-NEXT: r1:0 = vaddub(r3:2,r1:0)36; CHECK-NEXT: }37; CHECK-NEXT: {38; CHECK-NEXT: r5 = vtrunohb(r7:6)39; CHECK-NEXT: }40; CHECK-NEXT: {41; CHECK-NEXT: r1:0 = vsubub(r5:4,r1:0)42; CHECK-NEXT: }43; CHECK-NEXT: {44; CHECK-NEXT: jumpr r3145; CHECK-NEXT: }46 %v0 = sext <4 x i8> %a0 to <4 x i16>47 %v1 = sext <4 x i8> %a1 to <4 x i16>48 %v2 = mul <4 x i16> %v0, %v149 %v3 = lshr <4 x i16> %v2, <i16 8, i16 8, i16 8, i16 8>50 %v4 = trunc <4 x i16> %v3 to <4 x i8>51 ret <4 x i8> %v452}53 54define <4 x i8> @f1(<4 x i8> %a0, <4 x i8> %a1) #0 {55; CHECK-LABEL: f1:56; CHECK: // %bb.0:57; CHECK-NEXT: {58; CHECK-NEXT: r1:0 = vmpybu(r0,r1)59; CHECK-NEXT: }60; CHECK-NEXT: {61; CHECK-NEXT: r0 = vtrunohb(r1:0)62; CHECK-NEXT: }63; CHECK-NEXT: {64; CHECK-NEXT: jumpr r3165; CHECK-NEXT: }66 %v0 = zext <4 x i8> %a0 to <4 x i16>67 %v1 = zext <4 x i8> %a1 to <4 x i16>68 %v2 = mul <4 x i16> %v0, %v169 %v3 = lshr <4 x i16> %v2, <i16 8, i16 8, i16 8, i16 8>70 %v4 = trunc <4 x i16> %v3 to <4 x i8>71 ret <4 x i8> %v472}73 74define <8 x i8> @f2(<8 x i8> %a0, <8 x i8> %a1) #0 {75; CHECK-LABEL: f2:76; CHECK: // %bb.0:77; CHECK-NEXT: {78; CHECK-NEXT: r7:6 = combine(#0,#0)79; CHECK-NEXT: }80; CHECK-NEXT: {81; CHECK-NEXT: p0 = vcmpb.gt(r3:2,#-1)82; CHECK-NEXT: }83; CHECK-NEXT: {84; CHECK-NEXT: r5:4 = vmpybu(r0,r2)85; CHECK-NEXT: }86; CHECK-NEXT: {87; CHECK-NEXT: r9:8 = vmux(p0,r7:6,r1:0)88; CHECK-NEXT: }89; CHECK-NEXT: {90; CHECK-NEXT: p0 = vcmpb.gt(r1:0,#-1)91; CHECK-NEXT: }92; CHECK-NEXT: {93; CHECK-NEXT: r1:0 = vmpybu(r1,r3)94; CHECK-NEXT: }95; CHECK-NEXT: {96; CHECK-NEXT: r7:6 = vmux(p0,r7:6,r3:2)97; CHECK-NEXT: }98; CHECK-NEXT: {99; CHECK-NEXT: r4 = vtrunohb(r5:4)100; CHECK-NEXT: }101; CHECK-NEXT: {102; CHECK-NEXT: r3:2 = vaddub(r7:6,r9:8)103; CHECK-NEXT: }104; CHECK-NEXT: {105; CHECK-NEXT: r5 = vtrunohb(r1:0)106; CHECK-NEXT: }107; CHECK-NEXT: {108; CHECK-NEXT: r1:0 = vsubub(r5:4,r3:2)109; CHECK-NEXT: }110; CHECK-NEXT: {111; CHECK-NEXT: jumpr r31112; CHECK-NEXT: }113 %v0 = sext <8 x i8> %a0 to <8 x i16>114 %v1 = sext <8 x i8> %a1 to <8 x i16>115 %v2 = mul <8 x i16> %v0, %v1116 %v3 = lshr <8 x i16> %v2, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>117 %v4 = trunc <8 x i16> %v3 to <8 x i8>118 ret <8 x i8> %v4119}120 121define <8 x i8> @f3(<8 x i8> %a0, <8 x i8> %a1) #0 {122; CHECK-LABEL: f3:123; CHECK: // %bb.0:124; CHECK-NEXT: {125; CHECK-NEXT: r5:4 = vmpybu(r0,r2)126; CHECK-NEXT: }127; CHECK-NEXT: {128; CHECK-NEXT: r7:6 = vmpybu(r1,r3)129; CHECK-NEXT: }130; CHECK-NEXT: {131; CHECK-NEXT: r0 = vtrunohb(r5:4)132; CHECK-NEXT: }133; CHECK-NEXT: {134; CHECK-NEXT: r1 = vtrunohb(r7:6)135; CHECK-NEXT: }136; CHECK-NEXT: {137; CHECK-NEXT: jumpr r31138; CHECK-NEXT: }139 %v0 = zext <8 x i8> %a0 to <8 x i16>140 %v1 = zext <8 x i8> %a1 to <8 x i16>141 %v2 = mul <8 x i16> %v0, %v1142 %v3 = lshr <8 x i16> %v2, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>143 %v4 = trunc <8 x i16> %v3 to <8 x i8>144 ret <8 x i8> %v4145}146 147define <2 x i16> @f4(<2 x i16> %a0, <2 x i16> %a1) #0 {148; CHECK-LABEL: f4:149; CHECK: // %bb.0:150; CHECK-NEXT: {151; CHECK-NEXT: r1:0 = vmpyh(r0,r1):sat152; CHECK-NEXT: }153; CHECK-NEXT: {154; CHECK-NEXT: r0 = combine(r1.h,r0.h)155; CHECK-NEXT: }156; CHECK-NEXT: {157; CHECK-NEXT: jumpr r31158; CHECK-NEXT: }159 %v0 = sext <2 x i16> %a0 to <2 x i32>160 %v1 = sext <2 x i16> %a1 to <2 x i32>161 %v2 = mul <2 x i32> %v0, %v1162 %v3 = lshr <2 x i32> %v2, <i32 16, i32 16>163 %v4 = trunc <2 x i32> %v3 to <2 x i16>164 ret <2 x i16> %v4165}166 167define <2 x i16> @f5(<2 x i16> %a0, <2 x i16> %a1) #0 {168; CHECK-LABEL: f5:169; CHECK: // %bb.0:170; CHECK-NEXT: {171; CHECK-NEXT: r3:2 = combine(r0,r1)172; CHECK-NEXT: }173; CHECK-NEXT: {174; CHECK-NEXT: r1:0 = vasrh(r3:2,#15)175; CHECK-NEXT: }176; CHECK-NEXT: {177; CHECK-NEXT: r5:4 = vmpyh(r3,r2):sat178; CHECK-NEXT: }179; CHECK-NEXT: {180; CHECK-NEXT: r0 = and(r3,r0)181; CHECK-NEXT: }182; CHECK-NEXT: {183; CHECK-NEXT: r1 = and(r2,r1)184; CHECK-NEXT: }185; CHECK-NEXT: {186; CHECK-NEXT: r4 = combine(r5.h,r4.h)187; CHECK-NEXT: }188; CHECK-NEXT: {189; CHECK-NEXT: r0 = vaddh(r0,r1)190; CHECK-NEXT: }191; CHECK-NEXT: {192; CHECK-NEXT: r0 = vaddh(r4,r0)193; CHECK-NEXT: }194; CHECK-NEXT: {195; CHECK-NEXT: jumpr r31196; CHECK-NEXT: }197 %v0 = zext <2 x i16> %a0 to <2 x i32>198 %v1 = zext <2 x i16> %a1 to <2 x i32>199 %v2 = mul <2 x i32> %v0, %v1200 %v3 = lshr <2 x i32> %v2, <i32 16, i32 16>201 %v4 = trunc <2 x i32> %v3 to <2 x i16>202 ret <2 x i16> %v4203}204 205define <4 x i16> @f6(<4 x i16> %a0, <4 x i16> %a1) #0 {206; CHECK-LABEL: f6:207; CHECK: // %bb.0:208; CHECK-NEXT: {209; CHECK-NEXT: r5:4 = vmpyh(r0,r2):sat210; CHECK-NEXT: }211; CHECK-NEXT: {212; CHECK-NEXT: r7:6 = vmpyh(r1,r3):sat213; CHECK-NEXT: }214; CHECK-NEXT: {215; CHECK-NEXT: r0 = combine(r5.h,r4.h)216; CHECK-NEXT: }217; CHECK-NEXT: {218; CHECK-NEXT: r1 = combine(r7.h,r6.h)219; CHECK-NEXT: }220; CHECK-NEXT: {221; CHECK-NEXT: jumpr r31222; CHECK-NEXT: }223 %v0 = sext <4 x i16> %a0 to <4 x i32>224 %v1 = sext <4 x i16> %a1 to <4 x i32>225 %v2 = mul <4 x i32> %v0, %v1226 %v3 = lshr <4 x i32> %v2, <i32 16, i32 16, i32 16, i32 16>227 %v4 = trunc <4 x i32> %v3 to <4 x i16>228 ret <4 x i16> %v4229}230 231define <4 x i16> @f7(<4 x i16> %a0, <4 x i16> %a1) #0 {232; CHECK-LABEL: f7:233; CHECK: // %bb.0:234; CHECK-NEXT: {235; CHECK-NEXT: r7:6 = vasrh(r1:0,#15)236; CHECK-NEXT: }237; CHECK-NEXT: {238; CHECK-NEXT: r9:8 = vasrh(r3:2,#15)239; CHECK-NEXT: }240; CHECK-NEXT: {241; CHECK-NEXT: r5:4 = vmpyh(r0,r2):sat242; CHECK-NEXT: }243; CHECK-NEXT: {244; CHECK-NEXT: r7:6 = and(r3:2,r7:6)245; CHECK-NEXT: }246; CHECK-NEXT: {247; CHECK-NEXT: r3:2 = vmpyh(r1,r3):sat248; CHECK-NEXT: }249; CHECK-NEXT: {250; CHECK-NEXT: r1:0 = and(r1:0,r9:8)251; CHECK-NEXT: }252; CHECK-NEXT: {253; CHECK-NEXT: r4 = combine(r5.h,r4.h)254; CHECK-NEXT: }255; CHECK-NEXT: {256; CHECK-NEXT: r5 = combine(r3.h,r2.h)257; CHECK-NEXT: }258; CHECK-NEXT: {259; CHECK-NEXT: r1:0 = vaddh(r1:0,r7:6)260; CHECK-NEXT: }261; CHECK-NEXT: {262; CHECK-NEXT: r1:0 = vaddh(r5:4,r1:0)263; CHECK-NEXT: }264; CHECK-NEXT: {265; CHECK-NEXT: jumpr r31266; CHECK-NEXT: }267 %v0 = zext <4 x i16> %a0 to <4 x i32>268 %v1 = zext <4 x i16> %a1 to <4 x i32>269 %v2 = mul <4 x i32> %v0, %v1270 %v3 = lshr <4 x i32> %v2, <i32 16, i32 16, i32 16, i32 16>271 %v4 = trunc <4 x i32> %v3 to <4 x i16>272 ret <4 x i16> %v4273}274 275define <2 x i32> @f8(<2 x i32> %a0, <2 x i32> %a1) #0 {276; CHECK-LABEL: f8:277; CHECK: // %bb.0:278; CHECK-NEXT: {279; CHECK-NEXT: r0 = mpy(r0,r2)280; CHECK-NEXT: }281; CHECK-NEXT: {282; CHECK-NEXT: r1 = mpy(r1,r3)283; CHECK-NEXT: }284; CHECK-NEXT: {285; CHECK-NEXT: jumpr r31286; CHECK-NEXT: }287 %v0 = sext <2 x i32> %a0 to <2 x i64>288 %v1 = sext <2 x i32> %a1 to <2 x i64>289 %v2 = mul <2 x i64> %v0, %v1290 %v3 = lshr <2 x i64> %v2, <i64 32, i64 32>291 %v4 = trunc <2 x i64> %v3 to <2 x i32>292 ret <2 x i32> %v4293}294 295define <2 x i32> @f9(<2 x i32> %a0, <2 x i32> %a1) #0 {296; CHECK-LABEL: f9:297; CHECK: // %bb.0:298; CHECK-NEXT: {299; CHECK-NEXT: r0 = mpyu(r0,r2)300; CHECK-NEXT: }301; CHECK-NEXT: {302; CHECK-NEXT: r1 = mpyu(r1,r3)303; CHECK-NEXT: }304; CHECK-NEXT: {305; CHECK-NEXT: jumpr r31306; CHECK-NEXT: }307 %v0 = zext <2 x i32> %a0 to <2 x i64>308 %v1 = zext <2 x i32> %a1 to <2 x i64>309 %v2 = mul <2 x i64> %v0, %v1310 %v3 = lshr <2 x i64> %v2, <i64 32, i64 32>311 %v4 = trunc <2 x i64> %v3 to <2 x i32>312 ret <2 x i32> %v4313}314 315attributes #0 = { nounwind memory(none) "target-features"="-packets" }316