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1; RUN: llc -march=hexagon -debug-only=isel 2>&1 < %s - | FileCheck %s2; REQUIRES: asserts3 4; CHECK: [[R0:%[0-9]+]]:intregs = A2_tfrsi 05; CHECK-NEXT: predregs = C2_tfrrp killed [[R0]]:intregs6 7define fastcc i16 @test(ptr %0, { <4 x i32>, <4 x i1> } %1, <4 x i1> %2) {8Entry:9 %3 = alloca [16 x i8], i32 0, align 1610 %4 = alloca [16 x i8], i32 0, align 1611 store <4 x i32> <i32 1, i32 2, i32 3, i32 4>, ptr %4, align 1612 store <4 x i32> <i32 5, i32 6, i32 7, i32 8>, ptr %3, align 1613 %5 = load <4 x i32>, ptr %4, align 1614 %6 = load <4 x i32>, ptr %3, align 1615 %7 = call { <4 x i32>, <4 x i1> } @llvm.sadd.with.overflow.v4i32(<4 x i32> %5, <4 x i32> %6)16 %8 = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> %2)17 br i1 %8, label %OverflowFail, label %OverflowOk18 19OverflowFail: ; preds = %Entry20 store volatile i32 0, ptr null, align 421 unreachable22 23OverflowOk: ; preds = %Entry24 %9 = extractvalue { <4 x i32>, <4 x i1> } %7, 025 store <4 x i32> %9, ptr %0, align 1626 ret i16 027 }28 29declare { <4 x i32>, <4 x i1> } @llvm.sadd.with.overflow.v4i32(<4 x i32>, <4 x i32>) #030declare i1 @llvm.vector.reduce.or.v4i1(<4 x i1>) #031