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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=hexagon -hexagon-expand-condsets=0 < %s | FileCheck %s3 4define <4 x i8> @f0(<4 x i8> %a0, <4 x i8> %a1, i32 %a2) #0 {5; CHECK-LABEL: f0:6; CHECK: // %bb.0:7; CHECK-NEXT: {8; CHECK-NEXT: p0 = cmp.eq(r2,#0)9; CHECK-NEXT: }10; CHECK-NEXT: {11; CHECK-NEXT: r0 = mux(p0,r0,r1)12; CHECK-NEXT: jumpr r3113; CHECK-NEXT: }14 %v0 = icmp eq i32 %a2, 015 %v1 = select i1 %v0, <4 x i8> %a0, <4 x i8> %a116 ret <4 x i8> %v117}18 19define <8 x i8> @f1(<8 x i8> %a0, <8 x i8> %a1, i32 %a2) #0 {20; CHECK-LABEL: f1:21; CHECK: // %bb.0:22; CHECK-NEXT: {23; CHECK-NEXT: p0 = cmp.eq(r4,#0)24; CHECK-NEXT: }25; CHECK-NEXT: {26; CHECK-NEXT: r0 = mux(p0,r0,r2)27; CHECK-NEXT: jumpr r3128; CHECK-NEXT: r1 = mux(p0,r1,r3)29; CHECK-NEXT: }30 %v0 = icmp eq i32 %a2, 031 %v1 = select i1 %v0, <8 x i8> %a0, <8 x i8> %a132 ret <8 x i8> %v133}34 35define <2 x i16> @f2(<2 x i16> %a0, <2 x i16> %a1, i32 %a2) #0 {36; CHECK-LABEL: f2:37; CHECK: // %bb.0:38; CHECK-NEXT: {39; CHECK-NEXT: p0 = cmp.eq(r2,#0)40; CHECK-NEXT: }41; CHECK-NEXT: {42; CHECK-NEXT: r0 = mux(p0,r0,r1)43; CHECK-NEXT: jumpr r3144; CHECK-NEXT: }45 %v0 = icmp eq i32 %a2, 046 %v1 = select i1 %v0, <2 x i16> %a0, <2 x i16> %a147 ret <2 x i16> %v148}49 50define <4 x i16> @f3(<4 x i16> %a0, <4 x i16> %a1, i32 %a2) #0 {51; CHECK-LABEL: f3:52; CHECK: // %bb.0:53; CHECK-NEXT: {54; CHECK-NEXT: p0 = cmp.eq(r4,#0)55; CHECK-NEXT: }56; CHECK-NEXT: {57; CHECK-NEXT: r0 = mux(p0,r0,r2)58; CHECK-NEXT: jumpr r3159; CHECK-NEXT: r1 = mux(p0,r1,r3)60; CHECK-NEXT: }61 %v0 = icmp eq i32 %a2, 062 %v1 = select i1 %v0, <4 x i16> %a0, <4 x i16> %a163 ret <4 x i16> %v164}65 66define <2 x i32> @f4(<2 x i32> %a0, <2 x i32> %a1, i32 %a2) #0 {67; CHECK-LABEL: f4:68; CHECK: // %bb.0:69; CHECK-NEXT: {70; CHECK-NEXT: p0 = cmp.eq(r4,#0)71; CHECK-NEXT: }72; CHECK-NEXT: {73; CHECK-NEXT: r0 = mux(p0,r0,r2)74; CHECK-NEXT: jumpr r3175; CHECK-NEXT: r1 = mux(p0,r1,r3)76; CHECK-NEXT: }77 %v0 = icmp eq i32 %a2, 078 %v1 = select i1 %v0, <2 x i32> %a0, <2 x i32> %a179 ret <2 x i32> %v180}81 82attributes #0 = { nounwind }83