60 lines · plain
1; RUN: llc -mtriple=hexagon < %s | FileCheck %s2; RUN: llc --mtriple=hexagon -mattr=+hvxv79,+hvx-length128b < %s | FileCheck %s3 4define void @f0(<2 x i32> %a0, ptr %a1) {5; CHECK-LABEL: f0:6; CHECK: r[[REG1H:([0-9]+)]]:[[REG1L:([0-9]+)]] = combine(#1,#1)7; CHECK: r[[REG2H:([0-9]+)]]:[[REG2L:([0-9]+)]] = and(r[[REG2H]]:[[REG2L]],r[[REG1H]]:[[REG1L]])8; CHECK: p{{[0-9]+}} = vcmpw.eq(r[[REG2H]]:[[REG2L]],#1)9b0:10 %v0 = trunc <2 x i32> %a0 to <2 x i1>11 store <2 x i1> %v0, ptr %a1, align 112 ret void13}14 15define void @f1(<4 x i16> %a0, ptr %a1) {16; CHECK-LABEL: f1:17; CHECK: [[REG0:r([0-9]+)]] = and([[REG0]],##65537)18; CHECK: [[REG1:r([0-9]+)]] = and([[REG1]],##65537)19; CHECK: p{{[0-9]+}} = vcmph.eq(r{{[0-9]+}}:{{[0-9]+}},#1)20b0:21 %v0 = trunc <4 x i16> %a0 to <4 x i1>22 store <4 x i1> %v0, ptr %a1, align 123 ret void24}25 26define void @f2(<8 x i8> %a0, ptr %a1) {27; CHECK-LABEL: f2:28; CHECK: [[REG0:r([0-9]+)]] = and([[REG0]],##16843009)29; CHECK: [[REG1:r([0-9]+)]] = and([[REG1]],##16843009)30; CHECK: p{{[0-9]+}} = vcmpb.eq(r{{[0-9]+}}:{{[0-9]+}},#1)31b0:32 %v0 = trunc <8 x i8> %a0 to <8 x i1>33 store <8 x i1> %v0, ptr %a1, align 134 ret void35}36 37define void @f3(<4 x i8> %a0, ptr %a1) {38; CHECK-LABEL: f3:39; CHECK: r[[REGH:([0-9]+)]]:[[REGL:([0-9]+)]] = vzxtbh(r{{[0-9]+}})40; CHECK: r[[REGL]] = and(r[[REGL]],##65537)41; CHECK: r[[REGH]] = and(r[[REGH]],##65537)42; CHECK: p{{[0-9]+}} = vcmph.eq(r[[REGH]]:[[REGL]],#1)43b0:44 %v0 = trunc <4 x i8> %a0 to <4 x i1>45 store <4 x i1> %v0, ptr %a1, align 146 ret void47}48 49define void @f4(<2 x i16> %a0, ptr %a1) {50; CHECK-LABEL: f4:51; CHECK: r[[REGH:([0-9]+)]]:[[REGL:([0-9]+)]] = vzxthw(r{{[0-9]+}})52; CHECK: r[[REG1H:([0-9]+)]]:[[REG1L:([0-9]+)]] = combine(#1,#1)53; CHECK: r[[REGH]]:[[REGL]] = and(r[[REGH]]:[[REGL]],r[[REG1H]]:[[REG1L]])54; CHECK: p{{[0-9]+}} = vcmpw.eq(r[[REGH]]:[[REGL]],#1)55b0:56 %v0 = trunc <2 x i16> %a0 to <2 x i1>57 store <2 x i1> %v0, ptr %a1, align 158 ret void59}60