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1; RUN: llc -mtriple=hexagon -disable-hsdr -terminal-rule=0 < %s | FileCheck %s2 3; Check if instruction vandqrt.acc and its predecessor are scheduled in consecutive packets.4; CHECK: or(q{{[0-3]+}},q{{[0-3]+}})5; CHECK: }6; CHECK-NOT: }7; CHECK: |= vand(q{{[0-3]+}},r{{[0-9]+}})8; CHECK: endloop09 10target triple = "hexagon-unknown-linux-gnu"11 12; Function Attrs: nounwind13define void @f0(ptr noalias nocapture readonly %a0, i32 %a1, i32 %a2, i32 %a3, ptr noalias nocapture %a4, i32 %a5) #0 {14b0:15 %v0 = mul i32 %a2, 316 %v2 = mul i32 %a5, -217 %v3 = add i32 %v2, %a118 %v4 = and i32 %a5, 6319 %v5 = add i32 %v3, %v420 %v6 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 -1)21 %v7 = lshr i32 %v5, 622 %v8 = and i32 %v7, 723 %v9 = and i32 %v5, 51124 %v10 = icmp eq i32 %v9, 025 %v11 = shl i32 -1, %v826 %v12 = select i1 %v10, i32 0, i32 %v1127 %v13 = tail call i32 @llvm.hexagon.S2.vsplatrb(i32 %v12)28 %v14 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 %v13)29 %v15 = tail call <16 x i32> @llvm.hexagon.V6.vnot(<16 x i32> %v14)30 %v16 = tail call <64 x i1> @llvm.hexagon.V6.pred.scalar2(i32 %v5)31 %v17 = shl i32 1, %v832 %v18 = tail call i32 @llvm.hexagon.S2.vsplatrb(i32 %v17)33 %v19 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt.acc(<16 x i32> %v15, <64 x i1> %v16, i32 %v18)34 %v20 = tail call i32 @llvm.hexagon.S2.vsplatrb(i32 %a3)35 %v21 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 %v20)36 %v22 = icmp sgt i32 %v5, 037 br i1 %v22, label %b1, label %b838 39b1: ; preds = %b040 %v23 = getelementptr inbounds i8, ptr %a0, i32 %a541 %v25 = load <16 x i32>, ptr %v23, align 64, !tbaa !042 %v26 = add i32 %a5, 6443 %v27 = getelementptr inbounds i8, ptr %a0, i32 %v2644 %v29 = add i32 %a5, -6445 %v30 = getelementptr inbounds i8, ptr %a0, i32 %v2946 %v32 = load <16 x i32>, ptr %v30, align 64, !tbaa !047 %v33 = tail call <64 x i1> @llvm.hexagon.V6.pred.scalar2(i32 %a5)48 %v34 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %v33, i32 16843009)49 %v35 = tail call <16 x i32> @llvm.hexagon.V6.vnot(<16 x i32> %v34)50 %v36 = add i32 %v0, %a551 %v37 = getelementptr inbounds i8, ptr %a0, i32 %v3652 %v39 = sub i32 %a5, %v053 %v40 = getelementptr inbounds i8, ptr %a0, i32 %v3954 %v42 = tail call <16 x i32> @llvm.hexagon.V6.vd0()55 %v43 = add i32 %v4, %a156 %v44 = mul i32 %a5, 257 %v45 = sub i32 %v43, %v4458 %v46 = xor i32 %v45, -159 %v47 = icmp sgt i32 %v46, -51360 %v48 = select i1 %v47, i32 %v46, i32 -51361 %v49 = add i32 %v48, %a162 %v50 = add i32 %v49, %v463 %v51 = add i32 %v50, 51264 %v52 = sub i32 %v51, %v4465 %v53 = lshr i32 %v52, 966 %v54 = mul nuw nsw i32 %v53, 1667 %v55 = add nuw nsw i32 %v54, 1668 %v56 = getelementptr i32, ptr %a4, i32 %v5569 br label %b270 71b2: ; preds = %b6, %b172 %v57 = phi i32 [ %v46, %b1 ], [ %v125, %b6 ]73 %v58 = phi i32 [ %v5, %b1 ], [ %v123, %b6 ]74 %v59 = phi ptr [ %a4, %b1 ], [ %v122, %b6 ]75 %v60 = phi ptr [ %v37, %b1 ], [ %v114, %b6 ]76 %v61 = phi ptr [ %v40, %b1 ], [ %v115, %b6 ]77 %v62 = phi ptr [ %v27, %b1 ], [ %v116, %b6 ]78 %v63 = phi i32 [ 512, %b1 ], [ %v69, %b6 ]79 %v64 = phi i32 [ -2139062144, %b1 ], [ %v117, %b6 ]80 %v65 = phi <16 x i32> [ %v32, %b1 ], [ %v118, %b6 ]81 %v66 = phi <16 x i32> [ %v25, %b1 ], [ %v119, %b6 ]82 %v67 = phi <16 x i32> [ %v35, %b1 ], [ %v6, %b6 ]83 %v68 = icmp slt i32 %v58, %v6384 %v69 = select i1 %v68, i32 %v58, i32 %v6385 %v70 = icmp sgt i32 %v69, 086 br i1 %v70, label %b3, label %b687 88b3: ; preds = %b289 %v71 = xor i32 %v63, -190 %v72 = icmp sgt i32 %v57, %v7191 %v73 = select i1 %v72, i32 %v57, i32 %v7192 %v74 = icmp sgt i32 %v73, -6593 %v75 = add i32 %v73, 6394 %v76 = select i1 %v74, i32 %v75, i32 -295 %v77 = sub i32 %v76, %v7396 %v78 = lshr i32 %v77, 697 br label %b498 99b4: ; preds = %b4, %b3100 %v79 = phi i32 [ %v69, %b3 ], [ %v108, %b4 ]101 %v80 = phi ptr [ %v60, %b3 ], [ %v89, %b4 ]102 %v81 = phi ptr [ %v61, %b3 ], [ %v87, %b4 ]103 %v82 = phi ptr [ %v62, %b3 ], [ %v92, %b4 ]104 %v83 = phi i32 [ %v64, %b3 ], [ %v106, %b4 ]105 %v84 = phi <16 x i32> [ %v65, %b3 ], [ %v85, %b4 ]106 %v85 = phi <16 x i32> [ %v66, %b3 ], [ %v93, %b4 ]107 %v86 = phi <16 x i32> [ %v42, %b3 ], [ %v107, %b4 ]108 %v87 = getelementptr inbounds <16 x i32>, ptr %v81, i32 1109 %v88 = load <16 x i32>, ptr %v81, align 64, !tbaa !0110 %v89 = getelementptr inbounds <16 x i32>, ptr %v80, i32 1111 %v90 = load <16 x i32>, ptr %v80, align 64, !tbaa !0112 %v91 = tail call <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32> %v85, <16 x i32> %v84, i32 3)113 %v92 = getelementptr inbounds <16 x i32>, ptr %v82, i32 1114 %v93 = load <16 x i32>, ptr %v82, align 64, !tbaa !0115 %v94 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v93, <16 x i32> %v85, i32 3)116 %v95 = tail call <16 x i32> @llvm.hexagon.V6.vsububsat(<16 x i32> %v85, <16 x i32> %v21)117 %v96 = tail call <16 x i32> @llvm.hexagon.V6.vaddubsat(<16 x i32> %v85, <16 x i32> %v21)118 %v97 = tail call <16 x i32> @llvm.hexagon.V6.vmaxub(<16 x i32> %v88, <16 x i32> %v90)119 %v98 = tail call <16 x i32> @llvm.hexagon.V6.vminub(<16 x i32> %v88, <16 x i32> %v90)120 %v99 = tail call <16 x i32> @llvm.hexagon.V6.vmaxub(<16 x i32> %v94, <16 x i32> %v91)121 %v100 = tail call <16 x i32> @llvm.hexagon.V6.vminub(<16 x i32> %v94, <16 x i32> %v91)122 %v101 = tail call <16 x i32> @llvm.hexagon.V6.vminub(<16 x i32> %v97, <16 x i32> %v99)123 %v102 = tail call <16 x i32> @llvm.hexagon.V6.vmaxub(<16 x i32> %v98, <16 x i32> %v100)124 %v103 = tail call <64 x i1> @llvm.hexagon.V6.vgtub(<16 x i32> %v101, <16 x i32> %v96)125 %v104 = tail call <64 x i1> @llvm.hexagon.V6.vgtub(<16 x i32> %v95, <16 x i32> %v102)126 %v105 = tail call <64 x i1> @llvm.hexagon.V6.pred.or(<64 x i1> %v103, <64 x i1> %v104)127 %v106 = tail call i32 @llvm.hexagon.S6.rol.i.r(i32 %v83, i32 1)128 %v107 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt.acc(<16 x i32> %v86, <64 x i1> %v105, i32 %v106)129 %v108 = add nsw i32 %v79, -64130 %v109 = icmp sgt i32 %v79, 64131 br i1 %v109, label %b4, label %b5132 133b5: ; preds = %b4134 %v110 = add nuw nsw i32 %v78, 1135 %v111 = getelementptr <16 x i32>, ptr %v62, i32 %v110136 %v112 = getelementptr <16 x i32>, ptr %v60, i32 %v110137 %v113 = getelementptr <16 x i32>, ptr %v61, i32 %v110138 br label %b6139 140b6: ; preds = %b5, %b2141 %v114 = phi ptr [ %v112, %b5 ], [ %v60, %b2 ]142 %v115 = phi ptr [ %v113, %b5 ], [ %v61, %b2 ]143 %v116 = phi ptr [ %v111, %b5 ], [ %v62, %b2 ]144 %v117 = phi i32 [ %v106, %b5 ], [ %v64, %b2 ]145 %v118 = phi <16 x i32> [ %v85, %b5 ], [ %v65, %b2 ]146 %v119 = phi <16 x i32> [ %v93, %b5 ], [ %v66, %b2 ]147 %v120 = phi <16 x i32> [ %v107, %b5 ], [ %v42, %b2 ]148 %v121 = tail call <16 x i32> @llvm.hexagon.V6.vand(<16 x i32> %v120, <16 x i32> %v67)149 %v122 = getelementptr inbounds <16 x i32>, ptr %v59, i32 1150 store <16 x i32> %v121, ptr %v59, align 64, !tbaa !0151 %v123 = add nsw i32 %v58, -512152 %v124 = icmp sgt i32 %v58, 512153 %v125 = add i32 %v57, 512154 br i1 %v124, label %b2, label %b7155 156b7: ; preds = %b6157 br label %b8158 159b8: ; preds = %b7, %b0160 %v127 = phi ptr [ %v56, %b7 ], [ %a4, %b0 ]161 %v128 = getelementptr inbounds <16 x i32>, ptr %v127, i32 -1162 %v129 = load <16 x i32>, ptr %v128, align 64, !tbaa !0163 %v130 = tail call <16 x i32> @llvm.hexagon.V6.vand(<16 x i32> %v129, <16 x i32> %v19)164 store <16 x i32> %v130, ptr %v128, align 64, !tbaa !0165 ret void166}167 168; Function Attrs: nounwind readnone169declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #1170 171; Function Attrs: nounwind readnone172declare <16 x i32> @llvm.hexagon.V6.vnot(<16 x i32>) #1173 174; Function Attrs: nounwind readnone175declare <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1>, i32) #1176 177; Function Attrs: nounwind readnone178declare <64 x i1> @llvm.hexagon.V6.pred.scalar2(i32) #1179 180; Function Attrs: nounwind readnone181declare i32 @llvm.hexagon.S2.vsplatrb(i32) #1182 183; Function Attrs: nounwind readnone184declare <16 x i32> @llvm.hexagon.V6.vandqrt.acc(<16 x i32>, <64 x i1>, i32) #1185 186; Function Attrs: nounwind readnone187declare <16 x i32> @llvm.hexagon.V6.vd0() #1188 189; Function Attrs: nounwind readnone190declare <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32>, <16 x i32>, i32) #1191 192; Function Attrs: nounwind readnone193declare <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32>, <16 x i32>, i32) #1194 195; Function Attrs: nounwind readnone196declare <16 x i32> @llvm.hexagon.V6.vsububsat(<16 x i32>, <16 x i32>) #1197 198; Function Attrs: nounwind readnone199declare <16 x i32> @llvm.hexagon.V6.vaddubsat(<16 x i32>, <16 x i32>) #1200 201; Function Attrs: nounwind readnone202declare <16 x i32> @llvm.hexagon.V6.vmaxub(<16 x i32>, <16 x i32>) #1203 204; Function Attrs: nounwind readnone205declare <16 x i32> @llvm.hexagon.V6.vminub(<16 x i32>, <16 x i32>) #1206 207; Function Attrs: nounwind readnone208declare <64 x i1> @llvm.hexagon.V6.vgtub(<16 x i32>, <16 x i32>) #1209 210; Function Attrs: nounwind readnone211declare <64 x i1> @llvm.hexagon.V6.pred.or(<64 x i1>, <64 x i1>) #1212 213; Function Attrs: nounwind readnone214declare i32 @llvm.hexagon.S6.rol.i.r(i32, i32) #1215 216; Function Attrs: nounwind readnone217declare <16 x i32> @llvm.hexagon.V6.vand(<16 x i32>, <16 x i32>) #1218 219attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }220attributes #1 = { nounwind readnone }221 222!0 = !{!1, !1, i64 0}223!1 = !{!"omnipotent char", !2, i64 0}224!2 = !{!"Simple C/C++ TBAA"}225