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1; RUN: llc -mtriple=hexagon -O3 -hexagon-small-data-threshold=0 < %s | FileCheck %s2; Check that absolute loads are generated for 64-bit3 4target triple = "hexagon-unknown--elf"5 6@g0 = external global i8, align 87@g1 = external global i16, align 88@g2 = external global i32, align 89@g3 = external global i64, align 810 11; CHECK-LABEL: f0:12; CHECK: = memd(##441656)13define i64 @f0() #0 {14b0:15 %v0 = load volatile i64, ptr inttoptr (i32 441656 to ptr)16 ret i64 %v017}18 19; CHECK-LABEL: f1:20; CHECK: = memw(##441656)21define i64 @f1() #0 {22b0:23 %v0 = load volatile i32, ptr inttoptr (i32 441656 to ptr)24 %v1 = sext i32 %v0 to i6425 ret i64 %v126}27 28; CHECK-LABEL: f2:29; CHECK: = memw(##441656)30define i64 @f2() #0 {31b0:32 %v0 = load volatile i32, ptr inttoptr (i32 441656 to ptr)33 %v1 = zext i32 %v0 to i6434 ret i64 %v135}36 37; CHECK-LABEL: f3:38; CHECK: = memh(##441656)39define i64 @f3() #0 {40b0:41 %v0 = load volatile i16, ptr inttoptr (i32 441656 to ptr)42 %v1 = sext i16 %v0 to i6443 ret i64 %v144}45 46; CHECK-LABEL: f4:47; CHECK: = memuh(##441656)48define i64 @f4() #0 {49b0:50 %v0 = load volatile i16, ptr inttoptr (i32 441656 to ptr)51 %v1 = zext i16 %v0 to i6452 ret i64 %v153}54 55; CHECK-LABEL: f5:56; CHECK: = memb(##441656)57define i64 @f5() #0 {58b0:59 %v0 = load volatile i8, ptr inttoptr (i32 441656 to ptr)60 %v1 = sext i8 %v0 to i6461 ret i64 %v162}63 64; CHECK-LABEL: f6:65; CHECK: = memub(##441656)66define i64 @f6() #0 {67b0:68 %v0 = load volatile i8, ptr inttoptr (i32 441656 to ptr)69 %v1 = zext i8 %v0 to i6470 ret i64 %v171}72 73; CHECK-LABEL: f7:74; CHECK: = memd(##g3)75define i64 @f7() #0 {76b0:77 %v0 = load volatile i64, ptr @g378 ret i64 %v079}80 81; CHECK-LABEL: f8:82; CHECK: = memw(##g2)83define i64 @f8() #0 {84b0:85 %v0 = load volatile i32, ptr @g286 %v1 = sext i32 %v0 to i6487 ret i64 %v188}89 90; CHECK-LABEL: f9:91; CHECK: = memw(##g2)92define i64 @f9() #0 {93b0:94 %v0 = load volatile i32, ptr @g295 %v1 = zext i32 %v0 to i6496 ret i64 %v197}98 99; CHECK-LABEL: f10:100; CHECK: = memh(##g1)101define i64 @f10() #0 {102b0:103 %v0 = load volatile i16, ptr @g1104 %v1 = sext i16 %v0 to i64105 ret i64 %v1106}107 108; CHECK-LABEL: f11:109; CHECK: = memuh(##g1)110define i64 @f11() #0 {111b0:112 %v0 = load volatile i16, ptr @g1113 %v1 = zext i16 %v0 to i64114 ret i64 %v1115}116 117; CHECK-LABEL: f12:118; CHECK: = memb(##g0)119define i64 @f12() #0 {120b0:121 %v0 = load volatile i8, ptr @g0122 %v1 = sext i8 %v0 to i64123 ret i64 %v1124}125 126; CHECK-LABEL: f13:127; CHECK: = memub(##g0)128define i64 @f13() #0 {129b0:130 %v0 = load volatile i8, ptr @g0131 %v1 = zext i8 %v0 to i64132 ret i64 %v1133}134 135attributes #0 = { nounwind }136