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1; RUN: llc -mtriple=hexagon -O3 -hexagon-small-data-threshold=0 < %s | FileCheck %s2; This test checks the case if there are more than 2 uses of a constan address, move the3; value in to a register and replace all instances of constant with the register.4; The GenMemAbsolute pass generates a absolute-set instruction if there are more5; than 2 uses of this register.6 7; CHECK: loadi32_38; CHECK-NOT: r{{[0-9]+}} = memw(##441652)9; CHECK-NOT: r{{[0-9]+}} = memw(r{{[0-9]+}}+#0)10; CHECK:r{{[0-9]+}} = memw(r[[REG:[0-9]+]]=##441652)11; CHECK-NOT: r{{[0-9]+}} = {emw(##441652)12; CHECK:r{{[0-9]+}} = memw(r[[REG]]+#0)13; CHECK-NOT: r{{[0-9]+}} = memw(##441652)14; CHECK:r{{[0-9]+}} = memw(r[[REG]]+#0)15; CHECK-NOT: r{{[0-9]+}} = memw(##441652)16 17define void @loadi32_3() #0 {18entry:19 %0 = load volatile i32, ptr inttoptr (i32 441652 to ptr), align 420 %1 = load volatile i32, ptr inttoptr (i32 441652 to ptr), align 421 %2 = load volatile i32, ptr inttoptr (i32 441652 to ptr), align 422 ret void23}24 25; CHECK: loadi32_226; CHECK-NOT: r{{[0-9]+}} = ##44165227; CHECK: r{{[0-9]+}} = memw(##441652)28; CHECK: r{{[0-9]+}} = memw(##441652)29 30define void @loadi32_2() #0 {31entry:32 %0 = load volatile i32, ptr inttoptr (i32 441652 to ptr), align 433 %1 = load volatile i32, ptr inttoptr (i32 441652 to ptr), align 434 ret void35}36 37; CHECK: loadi32_abs_global_338; CHECK-NOT: r{{[0-9]+}} = memw(##globalInt)39; CHECK-NOT: r{{[0-9]+}} = memw(r{{[0-9]+}}+#0)40; CHECK:r{{[0-9]+}} = memw(r[[REG:[0-9]+]]=##globalInt)41; CHECK-NOT: r{{[0-9]+}} = memw(##globalInt)42; CHECK:r{{[0-9]+}} = memw(r[[REG]]+#0)43; CHECK-NOT: r{{[0-9]+}} = memw(##globalInt)44; CHECK:r{{[0-9]+}} = memw(r[[REG]]+#0)45; CHECK-NOT: r{{[0-9]+}} = memw(##globalInt)46 47@globalInt = external global i32, align 848define void @loadi32_abs_global_3() #0 {49entry:50 %0 = load volatile i32, ptr @globalInt, align 451 %1 = load volatile i32, ptr @globalInt, align 452 %2 = load volatile i32, ptr @globalInt, align 453 ret void54}55 56; CHECK: loadi32_abs_global_257; CHECK-NOT:r[[REG:[0-9]+]] = ##globalInt58; CHECK:r{{[0-9]+}} = memw(##globalInt)59; CHECK:r{{[0-9]+}} = memw(##globalInt)60 61define void @loadi32_abs_global_2() #0 {62entry:63 %0 = load volatile i32, ptr @globalInt, align 464 %1 = load volatile i32, ptr @globalInt, align 465 ret void66}67 68attributes #0 = { nounwind }69