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1; Run -O2 to make sure that all the usual optimizations do happen before2; the Hexagon loop idiom recognition runs. This is to check that we still3; get this opportunity regardless of what happens before.4 5; RUN: opt -O2 -S < %s | FileCheck %s6; RUN: opt -passes='default<O2>' -S < %s | FileCheck %s7 8target triple = "hexagon"9target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"10 11; CHECK-LABEL: define zeroext i16 @pmpy_mod_lsr12; There need to be two pmpy instructions.13; CHECK: call i64 @llvm.hexagon.M4.pmpyw14; CHECK: call i64 @llvm.hexagon.M4.pmpyw15 16define zeroext i16 @pmpy_mod_lsr(i8 zeroext %a0, i16 zeroext %a1) #0 {17b2:18 br label %b319 20b3: ; preds = %b44, %b221 %v4 = phi i8 [ %a0, %b2 ], [ %v19, %b44 ]22 %v5 = phi i16 [ %a1, %b2 ], [ %v43, %b44 ]23 %v6 = phi i8 [ 0, %b2 ], [ %v45, %b44 ]24 %v7 = zext i8 %v6 to i3225 %v8 = icmp slt i32 %v7, 826 br i1 %v8, label %b9, label %b4627 28b9: ; preds = %b329 %v10 = zext i8 %v4 to i3230 %v11 = and i32 %v10, 131 %v12 = trunc i16 %v5 to i832 %v13 = zext i8 %v12 to i3233 %v14 = and i32 %v13, 134 %v15 = xor i32 %v11, %v1435 %v16 = trunc i32 %v15 to i836 %v17 = zext i8 %v4 to i3237 %v18 = ashr i32 %v17, 138 %v19 = trunc i32 %v18 to i839 %v20 = zext i8 %v16 to i3240 %v21 = icmp eq i32 %v20, 141 br i1 %v21, label %b22, label %b2642 43b22: ; preds = %b944 %v23 = zext i16 %v5 to i3245 %v24 = xor i32 %v23, 1638646 %v25 = trunc i32 %v24 to i1647 br label %b2748 49b26: ; preds = %b950 br label %b2751 52b27: ; preds = %b26, %b2253 %v28 = phi i16 [ %v25, %b22 ], [ %v5, %b26 ]54 %v29 = phi i8 [ 1, %b22 ], [ 0, %b26 ]55 %v30 = zext i16 %v28 to i3256 %v31 = ashr i32 %v30, 157 %v32 = trunc i32 %v31 to i1658 %v33 = icmp ne i8 %v29, 059 br i1 %v33, label %b34, label %b3860 61b34: ; preds = %b2762 %v35 = zext i16 %v32 to i3263 %v36 = or i32 %v35, 3276864 %v37 = trunc i32 %v36 to i1665 br label %b4266 67b38: ; preds = %b2768 %v39 = zext i16 %v32 to i3269 %v40 = and i32 %v39, 3276770 %v41 = trunc i32 %v40 to i1671 br label %b4272 73b42: ; preds = %b38, %b3474 %v43 = phi i16 [ %v37, %b34 ], [ %v41, %b38 ]75 br label %b4476 77b44: ; preds = %b4278 %v45 = add i8 %v6, 179 br label %b380 81b46: ; preds = %b382 ret i16 %v583}84 85attributes #0 = { noinline nounwind "target-cpu"="hexagonv5" "target-features"="-hvx,-long-calls" }86