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1; RUN: llc -mtriple=hexagon -debug-only=isel < %s 2>&1 | FileCheck %s2; REQUIRES: asserts3 4; This test validates that ISel picks the correct equivalent of below mentioned intrinsics5; For S2_asr_i_r_rnd_goodsyntax:6; if (#u5 == 0) Assembler mapped to: Rd = Rs7; else Rd = asr(Rs,#u5-1):rnd8; For S2_asr_i_p_rnd_goodsyntax:9; if (#u6 == 0) Assembler mapped to: Rdd = combine(Rss.H32,Rss.L32)10; else Rdd = asr(Rss,#u6-1):rnd11; For S5_vasrhrnd_goodsyntax:12; if (#u4 == 0) Assembler mapped to: Rdd = combine(Rss.H32,Rss.L32)13; else Rdd = vasrh(Rss,#u4-1):raw14; For S5_asrhub_rnd_sat_goodsyntax:15; if (#u4 == 0) Assembler mapped to: Rd = vsathub(Rss)16; else Rd = vasrhub(Rss,#u4-1):raw17 18target triple = "hexagon-unknown--elf"19 20; CHECK-LABEL: f021; CHECK: ISEL: Starting selection on{{.*}}llvm.hexagon.S2.asr.i.r.rnd.goodsyntax22; CHECK: Morphed node{{.*}}A2_tfr23define i32 @f0(i32 %a0, i32 %a1) local_unnamed_addr #0 {24b0:25 %v0 = tail call i32 @llvm.hexagon.S2.asr.i.r.rnd.goodsyntax(i32 %a0, i32 0)26 %v1 = add i32 %v0, %a127 ret i32 %v128}29 30declare i32 @llvm.hexagon.S2.asr.i.r.rnd.goodsyntax(i32, i32) #131 32; CHECK-LABEL: f133; CHECK: ISEL: Starting selection on{{.*}}llvm.hexagon.S2.asr.i.r.rnd.goodsyntax34; CHECK: Morphed node{{.*}}S2_asr_i_r_rnd35define i32 @f1(i32 %a0, i32 %a1) local_unnamed_addr #0 {36b0:37 %v0 = tail call i32 @llvm.hexagon.S2.asr.i.r.rnd.goodsyntax(i32 %a0, i32 9)38 %v1 = add i32 %v0, %a139 ret i32 %v140}41 42; CHECK-LABEL: f243; CHECK: ISEL: Starting selection on{{.*}}llvm.hexagon.S2.asr.i.p.rnd.goodsyntax44; CHECK: Morphed node{{.*}}A2_combinew45define i64 @f2(i64 %a0, i32 %a1) local_unnamed_addr #0 {46b0:47 %v0 = zext i32 %a1 to i6448 %v1 = tail call i64 @llvm.hexagon.S2.asr.i.p.rnd.goodsyntax(i64 %a0, i32 0)49 %v2 = add nsw i64 %v1, %v050 ret i64 %v251}52 53declare i64 @llvm.hexagon.S2.asr.i.p.rnd.goodsyntax(i64, i32) #154 55; CHECK-LABEL: f356; CHECK: ISEL: Starting selection on{{.*}}llvm.hexagon.S2.asr.i.p.rnd.goodsyntax57; CHECK: Morphed node{{.*}}S2_asr_i_p_rnd58define i64 @f3(i64 %a0, i32 %a1) local_unnamed_addr #0 {59b0:60 %v0 = zext i32 %a1 to i6461 %v1 = tail call i64 @llvm.hexagon.S2.asr.i.p.rnd.goodsyntax(i64 %a0, i32 9)62 %v2 = add nsw i64 %v1, %v063 ret i64 %v264}65 66; CHECK-LABEL: f467; CHECK: ISEL: Starting selection on{{.*}}llvm.hexagon.S5.asrhub.rnd.sat.goodsyntax68; CHECK: Morphed node{{.*}}S2_vsathub69define i32 @f4(i64 %a0, i32 %a1) local_unnamed_addr #0 {70b0:71 %v0 = tail call i32 @llvm.hexagon.S5.asrhub.rnd.sat.goodsyntax(i64 %a0, i32 0)72 %v1 = add i32 %v0, %a173 ret i32 %v174}75 76declare i32 @llvm.hexagon.S5.asrhub.rnd.sat.goodsyntax(i64, i32) #177 78; CHECK-LABEL: f579; CHECK: ISEL: Starting selection on{{.*}}llvm.hexagon.S5.asrhub.rnd.sat.goodsyntax80; CHECK: Morphed node{{.*}}S5_asrhub_rnd_sat81define i32 @f5(i64 %a0, i32 %a1) local_unnamed_addr #0 {82b0:83 %v0 = tail call i32 @llvm.hexagon.S5.asrhub.rnd.sat.goodsyntax(i64 %a0, i32 9)84 %v1 = add i32 %v0, %a185 ret i32 %v186}87 88; CHECK-LABEL: f689; CHECK: ISEL: Starting selection on{{.*}}llvm.hexagon.S5.vasrhrnd.goodsyntax90; CHECK: Morphed node{{.*}}A2_combinew91define i64 @f6(i64 %a0, i32 %a1) local_unnamed_addr #0 {92b0:93 %v0 = zext i32 %a1 to i6494 %v1 = tail call i64 @llvm.hexagon.S5.vasrhrnd.goodsyntax(i64 %a0, i32 0)95 %v2 = add nsw i64 %v1, %v096 ret i64 %v297}98 99declare i64 @llvm.hexagon.S5.vasrhrnd.goodsyntax(i64, i32) #1100 101; CHECK-LABEL: f7102; CHECK: ISEL: Starting selection on{{.*}}llvm.hexagon.S5.vasrhrnd.goodsyntax103; CHECK: Morphed node{{.*}}S5_vasrhrnd104define i64 @f7(i64 %a0, i32 %a1) local_unnamed_addr #0 {105b0:106 %v0 = zext i32 %a1 to i64107 %v1 = tail call i64 @llvm.hexagon.S5.vasrhrnd.goodsyntax(i64 %a0, i32 9)108 %v2 = add nsw i64 %v1, %v0109 ret i64 %v2110}111 112attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" }113attributes #1 = { nounwind readnone }114