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1; RUN: llc -O2 -mtriple=hexagon < %s | FileCheck %s2; Test that we do generate max #u5 in memops.3; CHECK: memh(r{{[0-9]+}}+#0) -= #314 5@g0 = unnamed_addr global i16 -32, align 26 7; Function Attrs: norecurse nounwind8define fastcc void @f0() unnamed_addr #0 {9b0:10 %v0 = load i16, ptr @g0, align 1, !tbaa !411 %v1 = zext i16 %v0 to i3212 %v2 = mul nuw nsw i32 %v1, 962513 %v3 = and i32 %v2, 25514 %v4 = mul nuw nsw i32 %v3, 962515 %v5 = and i32 %v4, 25516 %v6 = trunc i32 %v5 to i1617 store i16 %v6, ptr @g0, align 2, !tbaa !418 ret void19}20 21define i32 @f1() {22b0:23 %v0 = load i16, ptr @g0, align 2, !tbaa !424 %v1 = zext i16 %v0 to i3225 %v2 = add nuw nsw i32 %v1, 6550526 %v3 = trunc i32 %v2 to i1627 store i16 %v3, ptr @g0, align 2, !tbaa !428 tail call fastcc void @f0()29 %v4 = load i16, ptr @g0, align 2, !tbaa !430 %v5 = zext i16 %v4 to i3231 ret i32 %v532}33 34attributes #0 = { norecurse nounwind "target-cpu"="hexagonv55" }35 36!llvm.module.flags = !{!0, !2}37 38!0 = !{i32 6, !"Target CPU", !1}39!1 = !{!"hexagonv55"}40!2 = !{i32 6, !"Target Features", !3}41!3 = !{!"-hvx"}42!4 = !{!5, !5, i64 0}43!5 = !{!"omnipotent char", !6, i64 0}44!6 = !{!"Simple C/C++ TBAA"}45