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1; RUN: llc -mtriple=hexagon < %s | FileCheck %s2 3@g0 = common global i8 0, align 14@g1 = common global i8 0, align 15@g2 = common global i16 0, align 26@g3 = common global i16 0, align 27@g4 = common global i32 0, align 48@g5 = common global i32 0, align 49 10; CHECK-LABEL: f0:11; CHECK: memb(r{{[0-9]+}}+#0) += #112define void @f0() #0 {13b0:14 %v0 = load i8, ptr @g0, align 1, !tbaa !015 %v1 = add i8 %v0, 116 store i8 %v1, ptr @g0, align 1, !tbaa !017 ret void18}19 20; CHECK-LABEL: f1:21; CHECK: memb(r{{[0-9]+}}+#0) -= #122define void @f1() #0 {23b0:24 %v0 = load i8, ptr @g0, align 1, !tbaa !025 %v1 = add i8 %v0, -126 store i8 %v1, ptr @g0, align 1, !tbaa !027 ret void28}29 30; CHECK-LABEL: f2:31; CHECK: memb(r{{[0-9]+}}+#0) += #532define void @f2() #0 {33b0:34 %v0 = load i8, ptr @g0, align 1, !tbaa !035 %v1 = zext i8 %v0 to i3236 %v2 = add nsw i32 %v1, 537 %v3 = trunc i32 %v2 to i838 store i8 %v3, ptr @g0, align 1, !tbaa !039 ret void40}41 42; CHECK-LABEL: f3:43; CHECK: memb(r{{[0-9]+}}+#0) -= #544define void @f3() #0 {45b0:46 %v0 = load i8, ptr @g0, align 1, !tbaa !047 %v1 = zext i8 %v0 to i3248 %v2 = add nsw i32 %v1, 25149 %v3 = trunc i32 %v2 to i850 store i8 %v3, ptr @g0, align 1, !tbaa !051 ret void52}53 54; CHECK-LABEL: f4:55; CHECK: memb(r{{[0-9]+}}+#0) -= #556define void @f4() #0 {57b0:58 %v0 = load i8, ptr @g0, align 1, !tbaa !059 %v1 = zext i8 %v0 to i3260 %v2 = add nsw i32 %v1, 25161 %v3 = trunc i32 %v2 to i862 store i8 %v3, ptr @g0, align 1, !tbaa !063 ret void64}65 66; CHECK-LABEL: f5:67; CHECK: memb(r{{[0-9]+}}+#0) += #568define void @f5() #0 {69b0:70 %v0 = load i8, ptr @g0, align 1, !tbaa !071 %v1 = zext i8 %v0 to i3272 %v2 = add nsw i32 %v1, 573 %v3 = trunc i32 %v2 to i874 store i8 %v3, ptr @g0, align 1, !tbaa !075 ret void76}77 78; CHECK-LABEL: f6:79; CHECK: memb(r{{[0-9]+}}+#0) += r{{[0-9]+}}80define void @f6(i8 zeroext %a0) #0 {81b0:82 %v0 = zext i8 %a0 to i3283 %v1 = load i8, ptr @g0, align 1, !tbaa !084 %v2 = zext i8 %v1 to i3285 %v3 = add nsw i32 %v2, %v086 %v4 = trunc i32 %v3 to i887 store i8 %v4, ptr @g0, align 1, !tbaa !088 ret void89}90 91; CHECK-LABEL: f7:92; CHECK: memb(r{{[0-9]+}}+#0) -= r{{[0-9]+}}93define void @f7(i8 zeroext %a0) #0 {94b0:95 %v0 = zext i8 %a0 to i3296 %v1 = load i8, ptr @g0, align 1, !tbaa !097 %v2 = zext i8 %v1 to i3298 %v3 = sub nsw i32 %v2, %v099 %v4 = trunc i32 %v3 to i8100 store i8 %v4, ptr @g0, align 1, !tbaa !0101 ret void102}103 104; CHECK-LABEL: f8:105; CHECK: memb(r{{[0-9]+}}+#0) |= r{{[0-9]+}}106define void @f8(i8 zeroext %a0) #0 {107b0:108 %v0 = load i8, ptr @g0, align 1, !tbaa !0109 %v1 = or i8 %v0, %a0110 store i8 %v1, ptr @g0, align 1, !tbaa !0111 ret void112}113 114; CHECK-LABEL: f9:115; CHECK: memb(r{{[0-9]+}}+#0) &= r{{[0-9]+}}116define void @f9(i8 zeroext %a0) #0 {117b0:118 %v0 = load i8, ptr @g0, align 1, !tbaa !0119 %v1 = and i8 %v0, %a0120 store i8 %v1, ptr @g0, align 1, !tbaa !0121 ret void122}123 124; CHECK-LABEL: f10:125; CHECK: memb(r{{[0-9]+}}+#0) = clrbit(#5)126define void @f10() #0 {127b0:128 %v0 = load i8, ptr @g0, align 1, !tbaa !0129 %v1 = zext i8 %v0 to i32130 %v2 = and i32 %v1, 223131 %v3 = trunc i32 %v2 to i8132 store i8 %v3, ptr @g0, align 1, !tbaa !0133 ret void134}135 136; CHECK-LABEL: f11:137; CHECK: memb(r{{[0-9]+}}+#0) = setbit(#7)138define void @f11() #0 {139b0:140 %v0 = load i8, ptr @g0, align 1, !tbaa !0141 %v1 = zext i8 %v0 to i32142 %v2 = or i32 %v1, 128143 %v3 = trunc i32 %v2 to i8144 store i8 %v3, ptr @g0, align 1, !tbaa !0145 ret void146}147 148; CHECK-LABEL: f12:149; CHECK: memb(r{{[0-9]+}}+#0) += #1150define void @f12() #0 {151b0:152 %v0 = load i8, ptr @g1, align 1, !tbaa !0153 %v1 = add i8 %v0, 1154 store i8 %v1, ptr @g1, align 1, !tbaa !0155 ret void156}157 158; CHECK-LABEL: f13:159; CHECK: memb(r{{[0-9]+}}+#0) -= #1160define void @f13() #0 {161b0:162 %v0 = load i8, ptr @g1, align 1, !tbaa !0163 %v1 = add i8 %v0, -1164 store i8 %v1, ptr @g1, align 1, !tbaa !0165 ret void166}167 168; CHECK-LABEL: f14:169; CHECK: memb(r{{[0-9]+}}+#0) += #5170define void @f14() #0 {171b0:172 %v0 = load i8, ptr @g1, align 1, !tbaa !0173 %v1 = zext i8 %v0 to i32174 %v2 = add nsw i32 %v1, 5175 %v3 = trunc i32 %v2 to i8176 store i8 %v3, ptr @g1, align 1, !tbaa !0177 ret void178}179 180; CHECK-LABEL: f15:181; CHECK: memb(r{{[0-9]+}}+#0) -= #5182define void @f15() #0 {183b0:184 %v0 = load i8, ptr @g1, align 1, !tbaa !0185 %v1 = zext i8 %v0 to i32186 %v2 = add nsw i32 %v1, 251187 %v3 = trunc i32 %v2 to i8188 store i8 %v3, ptr @g1, align 1, !tbaa !0189 ret void190}191 192; CHECK-LABEL: f16:193; CHECK: memb(r{{[0-9]+}}+#0) -= #5194define void @f16() #0 {195b0:196 %v0 = load i8, ptr @g1, align 1, !tbaa !0197 %v1 = zext i8 %v0 to i32198 %v2 = add nsw i32 %v1, 251199 %v3 = trunc i32 %v2 to i8200 store i8 %v3, ptr @g1, align 1, !tbaa !0201 ret void202}203 204; CHECK-LABEL: f17:205; CHECK: memb(r{{[0-9]+}}+#0) += #5206define void @f17() #0 {207b0:208 %v0 = load i8, ptr @g1, align 1, !tbaa !0209 %v1 = zext i8 %v0 to i32210 %v2 = add nsw i32 %v1, 5211 %v3 = trunc i32 %v2 to i8212 store i8 %v3, ptr @g1, align 1, !tbaa !0213 ret void214}215 216; CHECK-LABEL: f18:217; CHECK: memb(r{{[0-9]+}}+#0) += r{{[0-9]+}}218define void @f18(i8 signext %a0) #0 {219b0:220 %v0 = zext i8 %a0 to i32221 %v1 = load i8, ptr @g1, align 1, !tbaa !0222 %v2 = zext i8 %v1 to i32223 %v3 = add nsw i32 %v2, %v0224 %v4 = trunc i32 %v3 to i8225 store i8 %v4, ptr @g1, align 1, !tbaa !0226 ret void227}228 229; CHECK-LABEL: f19:230; CHECK: memb(r{{[0-9]+}}+#0) -= r{{[0-9]+}}231define void @f19(i8 signext %a0) #0 {232b0:233 %v0 = zext i8 %a0 to i32234 %v1 = load i8, ptr @g1, align 1, !tbaa !0235 %v2 = zext i8 %v1 to i32236 %v3 = sub nsw i32 %v2, %v0237 %v4 = trunc i32 %v3 to i8238 store i8 %v4, ptr @g1, align 1, !tbaa !0239 ret void240}241 242; CHECK-LABEL: f20:243; CHECK: memb(r{{[0-9]+}}+#0) |= r{{[0-9]+}}244define void @f20(i8 signext %a0) #0 {245b0:246 %v0 = load i8, ptr @g1, align 1, !tbaa !0247 %v1 = or i8 %v0, %a0248 store i8 %v1, ptr @g1, align 1, !tbaa !0249 ret void250}251 252; CHECK-LABEL: f21:253; CHECK: memb(r{{[0-9]+}}+#0) &= r{{[0-9]+}}254define void @f21(i8 signext %a0) #0 {255b0:256 %v0 = load i8, ptr @g1, align 1, !tbaa !0257 %v1 = and i8 %v0, %a0258 store i8 %v1, ptr @g1, align 1, !tbaa !0259 ret void260}261 262; CHECK-LABEL: f22:263; CHECK: memb(r{{[0-9]+}}+#0) = clrbit(#5)264define void @f22() #0 {265b0:266 %v0 = load i8, ptr @g1, align 1, !tbaa !0267 %v1 = zext i8 %v0 to i32268 %v2 = and i32 %v1, 223269 %v3 = trunc i32 %v2 to i8270 store i8 %v3, ptr @g1, align 1, !tbaa !0271 ret void272}273 274; CHECK-LABEL: f23:275; CHECK: memb(r{{[0-9]+}}+#0) = setbit(#7)276define void @f23() #0 {277b0:278 %v0 = load i8, ptr @g1, align 1, !tbaa !0279 %v1 = zext i8 %v0 to i32280 %v2 = or i32 %v1, 128281 %v3 = trunc i32 %v2 to i8282 store i8 %v3, ptr @g1, align 1, !tbaa !0283 ret void284}285 286; CHECK-LABEL: f24:287; CHECK: memh(r{{[0-9]+}}+#0) += #1288define void @f24() #0 {289b0:290 %v0 = load i16, ptr @g2, align 2, !tbaa !3291 %v1 = add i16 %v0, 1292 store i16 %v1, ptr @g2, align 2, !tbaa !3293 ret void294}295 296; CHECK-LABEL: f25:297; CHECK: memh(r{{[0-9]+}}+#0) -= #1298define void @f25() #0 {299b0:300 %v0 = load i16, ptr @g2, align 2, !tbaa !3301 %v1 = add i16 %v0, -1302 store i16 %v1, ptr @g2, align 2, !tbaa !3303 ret void304}305 306; CHECK-LABEL: f26:307; CHECK: memh(r{{[0-9]+}}+#0) += #5308define void @f26() #0 {309b0:310 %v0 = load i16, ptr @g2, align 2, !tbaa !3311 %v1 = zext i16 %v0 to i32312 %v2 = add nsw i32 %v1, 5313 %v3 = trunc i32 %v2 to i16314 store i16 %v3, ptr @g2, align 2, !tbaa !3315 ret void316}317 318; CHECK-LABEL: f27:319; CHECK: memh(r{{[0-9]+}}+#0) -= #5320define void @f27() #0 {321b0:322 %v0 = load i16, ptr @g2, align 2, !tbaa !3323 %v1 = zext i16 %v0 to i32324 %v2 = add nsw i32 %v1, 65531325 %v3 = trunc i32 %v2 to i16326 store i16 %v3, ptr @g2, align 2, !tbaa !3327 ret void328}329 330; CHECK-LABEL: f28:331; CHECK: memh(r{{[0-9]+}}+#0) -= #5332define void @f28() #0 {333b0:334 %v0 = load i16, ptr @g2, align 2, !tbaa !3335 %v1 = zext i16 %v0 to i32336 %v2 = add nsw i32 %v1, 65531337 %v3 = trunc i32 %v2 to i16338 store i16 %v3, ptr @g2, align 2, !tbaa !3339 ret void340}341 342; CHECK-LABEL: f29:343; CHECK: memh(r{{[0-9]+}}+#0) += #5344define void @f29() #0 {345b0:346 %v0 = load i16, ptr @g2, align 2, !tbaa !3347 %v1 = zext i16 %v0 to i32348 %v2 = add nsw i32 %v1, 5349 %v3 = trunc i32 %v2 to i16350 store i16 %v3, ptr @g2, align 2, !tbaa !3351 ret void352}353 354; CHECK-LABEL: f30:355; CHECK: memh(r{{[0-9]+}}+#0) += r{{[0-9]+}}356define void @f30(i16 zeroext %a0) #0 {357b0:358 %v0 = zext i16 %a0 to i32359 %v1 = load i16, ptr @g2, align 2, !tbaa !3360 %v2 = zext i16 %v1 to i32361 %v3 = add nsw i32 %v2, %v0362 %v4 = trunc i32 %v3 to i16363 store i16 %v4, ptr @g2, align 2, !tbaa !3364 ret void365}366 367; CHECK-LABEL: f31:368; CHECK: memh(r{{[0-9]+}}+#0) -= r{{[0-9]+}}369define void @f31(i16 zeroext %a0) #0 {370b0:371 %v0 = zext i16 %a0 to i32372 %v1 = load i16, ptr @g2, align 2, !tbaa !3373 %v2 = zext i16 %v1 to i32374 %v3 = sub nsw i32 %v2, %v0375 %v4 = trunc i32 %v3 to i16376 store i16 %v4, ptr @g2, align 2, !tbaa !3377 ret void378}379 380; CHECK-LABEL: f32:381; CHECK: memh(r{{[0-9]+}}+#0) |= r{{[0-9]+}}382define void @f32(i16 zeroext %a0) #0 {383b0:384 %v0 = load i16, ptr @g2, align 2, !tbaa !3385 %v1 = or i16 %v0, %a0386 store i16 %v1, ptr @g2, align 2, !tbaa !3387 ret void388}389 390; CHECK-LABEL: f33:391; CHECK: memh(r{{[0-9]+}}+#0) &= r{{[0-9]+}}392define void @f33(i16 zeroext %a0) #0 {393b0:394 %v0 = load i16, ptr @g2, align 2, !tbaa !3395 %v1 = and i16 %v0, %a0396 store i16 %v1, ptr @g2, align 2, !tbaa !3397 ret void398}399 400; CHECK-LABEL: f34:401; CHECK: memh(r{{[0-9]+}}+#0) = clrbit(#5)402define void @f34() #0 {403b0:404 %v0 = load i16, ptr @g2, align 2, !tbaa !3405 %v1 = zext i16 %v0 to i32406 %v2 = and i32 %v1, 65503407 %v3 = trunc i32 %v2 to i16408 store i16 %v3, ptr @g2, align 2, !tbaa !3409 ret void410}411 412; CHECK-LABEL: f35:413; CHECK: memh(r{{[0-9]+}}+#0) = setbit(#7)414define void @f35() #0 {415b0:416 %v0 = load i16, ptr @g2, align 2, !tbaa !3417 %v1 = zext i16 %v0 to i32418 %v2 = or i32 %v1, 128419 %v3 = trunc i32 %v2 to i16420 store i16 %v3, ptr @g2, align 2, !tbaa !3421 ret void422}423 424; CHECK-LABEL: f36:425; CHECK: memh(r{{[0-9]+}}+#0) += #1426define void @f36() #0 {427b0:428 %v0 = load i16, ptr @g3, align 2, !tbaa !3429 %v1 = add i16 %v0, 1430 store i16 %v1, ptr @g3, align 2, !tbaa !3431 ret void432}433 434; CHECK-LABEL: f37:435; CHECK: memh(r{{[0-9]+}}+#0) -= #1436define void @f37() #0 {437b0:438 %v0 = load i16, ptr @g3, align 2, !tbaa !3439 %v1 = add i16 %v0, -1440 store i16 %v1, ptr @g3, align 2, !tbaa !3441 ret void442}443 444; CHECK-LABEL: f38:445; CHECK: memh(r{{[0-9]+}}+#0) += #5446define void @f38() #0 {447b0:448 %v0 = load i16, ptr @g3, align 2, !tbaa !3449 %v1 = zext i16 %v0 to i32450 %v2 = add nsw i32 %v1, 5451 %v3 = trunc i32 %v2 to i16452 store i16 %v3, ptr @g3, align 2, !tbaa !3453 ret void454}455 456; CHECK-LABEL: f39:457; CHECK: memh(r{{[0-9]+}}+#0) -= #5458define void @f39() #0 {459b0:460 %v0 = load i16, ptr @g3, align 2, !tbaa !3461 %v1 = zext i16 %v0 to i32462 %v2 = add nsw i32 %v1, 65531463 %v3 = trunc i32 %v2 to i16464 store i16 %v3, ptr @g3, align 2, !tbaa !3465 ret void466}467 468; CHECK-LABEL: f40:469; CHECK: memh(r{{[0-9]+}}+#0) -= #5470define void @f40() #0 {471b0:472 %v0 = load i16, ptr @g3, align 2, !tbaa !3473 %v1 = zext i16 %v0 to i32474 %v2 = add nsw i32 %v1, 65531475 %v3 = trunc i32 %v2 to i16476 store i16 %v3, ptr @g3, align 2, !tbaa !3477 ret void478}479 480; CHECK-LABEL: f41481; CHECK: memh(r{{[0-9]+}}+#0) += #5482define void @f41() #0 {483b0:484 %v0 = load i16, ptr @g3, align 2, !tbaa !3485 %v1 = zext i16 %v0 to i32486 %v2 = add nsw i32 %v1, 5487 %v3 = trunc i32 %v2 to i16488 store i16 %v3, ptr @g3, align 2, !tbaa !3489 ret void490}491 492; CHECK-LABEL: f42493; CHECK: memh(r{{[0-9]+}}+#0) += r{{[0-9]+}}494define void @f42(i16 signext %a0) #0 {495b0:496 %v0 = zext i16 %a0 to i32497 %v1 = load i16, ptr @g3, align 2, !tbaa !3498 %v2 = zext i16 %v1 to i32499 %v3 = add nsw i32 %v2, %v0500 %v4 = trunc i32 %v3 to i16501 store i16 %v4, ptr @g3, align 2, !tbaa !3502 ret void503}504 505; CHECK-LABEL: f43506; CHECK: memh(r{{[0-9]+}}+#0) -= r{{[0-9]+}}507define void @f43(i16 signext %a0) #0 {508b0:509 %v0 = zext i16 %a0 to i32510 %v1 = load i16, ptr @g3, align 2, !tbaa !3511 %v2 = zext i16 %v1 to i32512 %v3 = sub nsw i32 %v2, %v0513 %v4 = trunc i32 %v3 to i16514 store i16 %v4, ptr @g3, align 2, !tbaa !3515 ret void516}517 518; CHECK-LABEL: f44519; CHECK: memh(r{{[0-9]+}}+#0) |= r{{[0-9]+}}520define void @f44(i16 signext %a0) #0 {521b0:522 %v0 = load i16, ptr @g3, align 2, !tbaa !3523 %v1 = or i16 %v0, %a0524 store i16 %v1, ptr @g3, align 2, !tbaa !3525 ret void526}527 528; CHECK-LABEL: f45529; CHECK: memh(r{{[0-9]+}}+#0) &= r{{[0-9]+}}530define void @f45(i16 signext %a0) #0 {531b0:532 %v0 = load i16, ptr @g3, align 2, !tbaa !3533 %v1 = and i16 %v0, %a0534 store i16 %v1, ptr @g3, align 2, !tbaa !3535 ret void536}537 538; CHECK-LABEL: f46539; CHECK: memh(r{{[0-9]+}}+#0) = clrbit(#5)540define void @f46() #0 {541b0:542 %v0 = load i16, ptr @g3, align 2, !tbaa !3543 %v1 = zext i16 %v0 to i32544 %v2 = and i32 %v1, 65503545 %v3 = trunc i32 %v2 to i16546 store i16 %v3, ptr @g3, align 2, !tbaa !3547 ret void548}549 550; CHECK-LABEL: f47551; CHECK: memh(r{{[0-9]+}}+#0) = setbit(#7)552define void @f47() #0 {553b0:554 %v0 = load i16, ptr @g3, align 2, !tbaa !3555 %v1 = zext i16 %v0 to i32556 %v2 = or i32 %v1, 128557 %v3 = trunc i32 %v2 to i16558 store i16 %v3, ptr @g3, align 2, !tbaa !3559 ret void560}561 562; CHECK-LABEL: f48563; CHECK: memw(r{{[0-9]+}}+#0) += #1564define void @f48() #0 {565b0:566 %v0 = load i32, ptr @g4, align 4, !tbaa !5567 %v1 = add nsw i32 %v0, 1568 store i32 %v1, ptr @g4, align 4, !tbaa !5569 ret void570}571 572; CHECK-LABEL: f49573; CHECK: memw(r{{[0-9]+}}+#0) -= #1574define void @f49() #0 {575b0:576 %v0 = load i32, ptr @g4, align 4, !tbaa !5577 %v1 = add nsw i32 %v0, -1578 store i32 %v1, ptr @g4, align 4, !tbaa !5579 ret void580}581 582; CHECK-LABEL: f50583; CHECK: memw(r{{[0-9]+}}+#0) += #5584define void @f50() #0 {585b0:586 %v0 = load i32, ptr @g4, align 4, !tbaa !5587 %v1 = add nsw i32 %v0, 5588 store i32 %v1, ptr @g4, align 4, !tbaa !5589 ret void590}591 592; CHECK-LABEL: f51593; CHECK: memw(r{{[0-9]+}}+#0) -= #5594define void @f51() #0 {595b0:596 %v0 = load i32, ptr @g4, align 4, !tbaa !5597 %v1 = add nsw i32 %v0, -5598 store i32 %v1, ptr @g4, align 4, !tbaa !5599 ret void600}601 602; CHECK-LABEL: f52603; CHECK: memw(r{{[0-9]+}}+#0) -= #5604define void @f52() #0 {605b0:606 %v0 = load i32, ptr @g4, align 4, !tbaa !5607 %v1 = add nsw i32 %v0, -5608 store i32 %v1, ptr @g4, align 4, !tbaa !5609 ret void610}611 612; CHECK-LABEL: f53613; CHECK: memw(r{{[0-9]+}}+#0) += #5614define void @f53() #0 {615b0:616 %v0 = load i32, ptr @g4, align 4, !tbaa !5617 %v1 = add nsw i32 %v0, 5618 store i32 %v1, ptr @g4, align 4, !tbaa !5619 ret void620}621 622; CHECK-LABEL: f54623; CHECK: memw(r{{[0-9]+}}+#0) += r{{[0-9]+}}624define void @f54(i32 %a0) #0 {625b0:626 %v0 = load i32, ptr @g4, align 4, !tbaa !5627 %v1 = add i32 %v0, %a0628 store i32 %v1, ptr @g4, align 4, !tbaa !5629 ret void630}631 632; CHECK-LABEL: f55633; CHECK: memw(r{{[0-9]+}}+#0) -= r{{[0-9]+}}634define void @f55(i32 %a0) #0 {635b0:636 %v0 = load i32, ptr @g4, align 4, !tbaa !5637 %v1 = sub i32 %v0, %a0638 store i32 %v1, ptr @g4, align 4, !tbaa !5639 ret void640}641 642; CHECK-LABEL: f56643; CHECK: memw(r{{[0-9]+}}+#0) |= r{{[0-9]+}}644define void @f56(i32 %a0) #0 {645b0:646 %v0 = load i32, ptr @g4, align 4, !tbaa !5647 %v1 = or i32 %v0, %a0648 store i32 %v1, ptr @g4, align 4, !tbaa !5649 ret void650}651 652; CHECK-LABEL: f57653; CHECK: memw(r{{[0-9]+}}+#0) &= r{{[0-9]+}}654define void @f57(i32 %a0) #0 {655b0:656 %v0 = load i32, ptr @g4, align 4, !tbaa !5657 %v1 = and i32 %v0, %a0658 store i32 %v1, ptr @g4, align 4, !tbaa !5659 ret void660}661 662; CHECK-LABEL: f58663; CHECK: memw(r{{[0-9]+}}+#0) = clrbit(#5)664define void @f58() #0 {665b0:666 %v0 = load i32, ptr @g4, align 4, !tbaa !5667 %v1 = and i32 %v0, -33668 store i32 %v1, ptr @g4, align 4, !tbaa !5669 ret void670}671 672; CHECK-LABEL: f59673; CHECK: memw(r{{[0-9]+}}+#0) = setbit(#7)674define void @f59() #0 {675b0:676 %v0 = load i32, ptr @g4, align 4, !tbaa !5677 %v1 = or i32 %v0, 128678 store i32 %v1, ptr @g4, align 4, !tbaa !5679 ret void680}681 682; CHECK-LABEL: f60683; CHECK: memw(r{{[0-9]+}}+#0) += #1684define void @f60() #0 {685b0:686 %v0 = load i32, ptr @g5, align 4, !tbaa !5687 %v1 = add i32 %v0, 1688 store i32 %v1, ptr @g5, align 4, !tbaa !5689 ret void690}691 692; CHECK-LABEL: f61693; CHECK: memw(r{{[0-9]+}}+#0) -= #1694define void @f61() #0 {695b0:696 %v0 = load i32, ptr @g5, align 4, !tbaa !5697 %v1 = add i32 %v0, -1698 store i32 %v1, ptr @g5, align 4, !tbaa !5699 ret void700}701 702; CHECK-LABEL: f62703; CHECK: memw(r{{[0-9]+}}+#0) += #5704define void @f62() #0 {705b0:706 %v0 = load i32, ptr @g5, align 4, !tbaa !5707 %v1 = add i32 %v0, 5708 store i32 %v1, ptr @g5, align 4, !tbaa !5709 ret void710}711 712; CHECK-LABEL: f63713; CHECK: memw(r{{[0-9]+}}+#0) -= #5714define void @f63() #0 {715b0:716 %v0 = load i32, ptr @g5, align 4, !tbaa !5717 %v1 = add i32 %v0, -5718 store i32 %v1, ptr @g5, align 4, !tbaa !5719 ret void720}721 722; CHECK-LABEL: f64723; CHECK: memw(r{{[0-9]+}}+#0) -= #5724define void @f64() #0 {725b0:726 %v0 = load i32, ptr @g5, align 4, !tbaa !5727 %v1 = add i32 %v0, -5728 store i32 %v1, ptr @g5, align 4, !tbaa !5729 ret void730}731 732; CHECK-LABEL: f65733; CHECK: memw(r{{[0-9]+}}+#0) += #5734define void @f65() #0 {735b0:736 %v0 = load i32, ptr @g5, align 4, !tbaa !5737 %v1 = add i32 %v0, 5738 store i32 %v1, ptr @g5, align 4, !tbaa !5739 ret void740}741 742; CHECK-LABEL: f66:743; CHECK: memw(r{{[0-9]+}}+#0) += r{{[0-9]+}}744define void @f66(i32 %a0) #0 {745b0:746 %v0 = load i32, ptr @g5, align 4, !tbaa !5747 %v1 = add i32 %v0, %a0748 store i32 %v1, ptr @g5, align 4, !tbaa !5749 ret void750}751 752; CHECK-LABEL: f67:753; CHECK: memw(r{{[0-9]+}}+#0) -= r{{[0-9]+}}754define void @f67(i32 %a0) #0 {755b0:756 %v0 = load i32, ptr @g5, align 4, !tbaa !5757 %v1 = sub i32 %v0, %a0758 store i32 %v1, ptr @g5, align 4, !tbaa !5759 ret void760}761 762; CHECK-LABEL: f68:763; CHECK: memw(r{{[0-9]+}}+#0) |= r{{[0-9]+}}764define void @f68(i32 %a0) #0 {765b0:766 %v0 = load i32, ptr @g5, align 4, !tbaa !5767 %v1 = or i32 %v0, %a0768 store i32 %v1, ptr @g5, align 4, !tbaa !5769 ret void770}771 772; CHECK-LABEL: f69:773; CHECK: memw(r{{[0-9]+}}+#0) &= r{{[0-9]+}}774define void @f69(i32 %a0) #0 {775b0:776 %v0 = load i32, ptr @g5, align 4, !tbaa !5777 %v1 = and i32 %v0, %a0778 store i32 %v1, ptr @g5, align 4, !tbaa !5779 ret void780}781 782; CHECK-LABEL: f70:783; CHECK: memw(r{{[0-9]+}}+#0) = clrbit(#5)784define void @f70() #0 {785b0:786 %v0 = load i32, ptr @g5, align 4, !tbaa !5787 %v1 = and i32 %v0, -33788 store i32 %v1, ptr @g5, align 4, !tbaa !5789 ret void790}791 792; CHECK-LABEL: f71:793; CHECK: memw(r{{[0-9]+}}+#0) = setbit(#7)794define void @f71() #0 {795b0:796 %v0 = load i32, ptr @g5, align 4, !tbaa !5797 %v1 = or i32 %v0, 128798 store i32 %v1, ptr @g5, align 4, !tbaa !5799 ret void800}801 802attributes #0 = { nounwind }803 804!0 = !{!1, !1, i64 0}805!1 = !{!"omnipotent char", !2}806!2 = !{!"Simple C/C++ TBAA"}807!3 = !{!4, !4, i64 0}808!4 = !{!"short", !1}809!5 = !{!6, !6, i64 0}810!6 = !{!"int", !1}811