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1; RUN: llc -mtriple=hexagon < %s2; Check that the mis-aligned load doesn't cause compiler to assert.3 4@g0 = common global i32 0, align 45 6declare i32 @f0(i64) #07 8define i32 @f1() #0 {9b0:10 %v0 = alloca i32, align 411 %v1 = load i32, ptr @g0, align 412 store i32 %v1, ptr %v0, align 413 %v3 = load i64, ptr %v0, align 814 %v4 = call i32 @f0(i64 %v3)15 ret i32 %v416}17 18attributes #0 = { nounwind "target-cpu"="hexagonv5" }19