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1; RUN: llc -mtriple=hexagon -O2 < %s | FileCheck %s2 3; CHECK: v{{[0-9]+}}.h = vadd(v{{[0-9]+}}.h,v{{[0-9]+}}.h)4; CHECK: }5; CHECK: {6; CHECK: v{{[0-9]+}} = valign(v{{[0-9]+}},v{{[0-9]+}},#2)7; CHECK: }8; CHECK: {9; CHECK: v{{[0-9]+}} = valign(v{{[0-9]+}},v{{[0-9]+}},#2)10 11target triple = "hexagon"12 13@ZERO = global <16 x i32> zeroinitializer, align 6414 15define void @fred(ptr nocapture readonly %a0, i32 %a1, i32 %a2, ptr nocapture %a3) #0 {16b4:17 %v6 = getelementptr inbounds i16, ptr %a0, i32 %a118 %v8 = mul nsw i32 %a1, 219 %v9 = getelementptr inbounds i16, ptr %a0, i32 %v820 %v11 = load <16 x i32>, ptr %a0, align 64, !tbaa !121 %v12 = load <16 x i32>, ptr %v6, align 64, !tbaa !122 %v13 = load <16 x i32>, ptr %v9, align 64, !tbaa !123 %v14 = load <16 x i32>, ptr @ZERO, align 64, !tbaa !124 %v15 = tail call <16 x i32> @llvm.hexagon.V6.vsubh(<16 x i32> %v14, <16 x i32> %v14)25 %v16 = sdiv i32 %a2, 3226 %v17 = icmp sgt i32 %a2, 3127 br i1 %v17, label %b18, label %b6628 29b18: ; preds = %b430 %v19 = add i32 %v8, 3231 %v20 = add i32 %a1, 3232 %v21 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v12, <16 x i32> %v12)33 %v22 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v11, <16 x i32> %v13)34 %v23 = getelementptr inbounds i16, ptr %a0, i32 %v1935 %v24 = getelementptr inbounds i16, ptr %a0, i32 %v2036 %v25 = getelementptr inbounds i16, ptr %a0, i32 3237 %v26 = tail call <16 x i32> @llvm.hexagon.V6.vsubh(<16 x i32> %v11, <16 x i32> %v13)38 %v27 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v22, <16 x i32> %v21)39 br label %b3240 41b32: ; preds = %b32, %b1842 %v33 = phi i32 [ 0, %b18 ], [ %v63, %b32 ]43 %v34 = phi ptr [ %a3, %b18 ], [ %v62, %b32 ]44 %v35 = phi ptr [ %v23, %b18 ], [ %v46, %b32 ]45 %v36 = phi ptr [ %v24, %b18 ], [ %v44, %b32 ]46 %v37 = phi ptr [ %v25, %b18 ], [ %v42, %b32 ]47 %v38 = phi <16 x i32> [ %v15, %b18 ], [ %v39, %b32 ]48 %v39 = phi <16 x i32> [ %v26, %b18 ], [ %v56, %b32 ]49 %v40 = phi <16 x i32> [ %v27, %b18 ], [ %v51, %b32 ]50 %v41 = phi <16 x i32> [ %v15, %b18 ], [ %v40, %b32 ]51 %v42 = getelementptr inbounds <16 x i32>, ptr %v37, i32 152 %v43 = load <16 x i32>, ptr %v37, align 64, !tbaa !153 %v44 = getelementptr inbounds <16 x i32>, ptr %v36, i32 154 %v45 = load <16 x i32>, ptr %v36, align 64, !tbaa !155 %v46 = getelementptr inbounds <16 x i32>, ptr %v35, i32 156 %v47 = load <16 x i32>, ptr %v35, align 64, !tbaa !157 %v48 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v43, <16 x i32> %v47)58 %v49 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v45, <16 x i32> %v45)59 %v50 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v40, <16 x i32> %v41, i32 62)60 %v51 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v48, <16 x i32> %v49)61 %v52 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v51, <16 x i32> %v40, i32 2)62 %v53 = tail call <16 x i32> @llvm.hexagon.V6.vabsdiffh(<16 x i32> %v50, <16 x i32> %v52)63 %v54 = getelementptr inbounds <16 x i32>, ptr %v34, i32 164 store <16 x i32> %v53, ptr %v34, align 64, !tbaa !165 %v55 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v39, <16 x i32> %v38, i32 62)66 %v56 = tail call <16 x i32> @llvm.hexagon.V6.vsubh(<16 x i32> %v43, <16 x i32> %v47)67 %v57 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v56, <16 x i32> %v39, i32 2)68 %v58 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v39, <16 x i32> %v39)69 %v59 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v58, <16 x i32> %v55)70 %v60 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v59, <16 x i32> %v57)71 %v61 = tail call <16 x i32> @llvm.hexagon.V6.vabsh(<16 x i32> %v60)72 %v62 = getelementptr inbounds <16 x i32>, ptr %v34, i32 273 store <16 x i32> %v61, ptr %v54, align 64, !tbaa !174 %v63 = add nsw i32 %v33, 175 %v64 = icmp slt i32 %v63, %v1676 br i1 %v64, label %b32, label %b6577 78b65: ; preds = %b3279 br label %b6680 81b66: ; preds = %b65, %b482 ret void83}84 85declare <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32>, <16 x i32>) #186declare <16 x i32> @llvm.hexagon.V6.vsubh(<16 x i32>, <16 x i32>) #187declare <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32>, <16 x i32>, i32) #188declare <16 x i32> @llvm.hexagon.V6.vabsdiffh(<16 x i32>, <16 x i32>) #189declare <16 x i32> @llvm.hexagon.V6.vabsh(<16 x i32>) #190 91attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }92attributes #1 = { nounwind readnone }93 94!1 = !{!2, !2, i64 0}95!2 = !{!"omnipotent char", !3, i64 0}96!3 = !{!"Simple C/C++ TBAA"}97